GEMM fp4 fp6 n2048 k2048
2 eligible runs
gemm
Unscaled mixed FP4(E2M1) x FP6(e3m2) narrow GEMM C = A @ B.T (N=2048, K=2048). A is packed E2M1 (int8, 2 fp4/byte); B is FP6 e3m2 stored as one 6-bit code per int8 byte. No block scales.
Source baseline · unbeaten
10.3msmean
cuda_fp4_fp6_naive_n2048_k2048FlashInfer-Bench baselines · Apache-2.0 · cuda
Reproduction-ready evidence · last observed 2026-06-06. The source's designated baseline implementation. Reported by source; not independently reproduced.
Current records
Not measured on H100 for this workload. Challenges →
Source-native comparison · GPU NVIDIA B200 · Workload m = 64 · int8 · CUDA 13.0 · Framework pytorch 2.11.0+cu130 · Protocol flashinfer-bench · mean · 1 results · last observed 2026-06-06Record history →
Estimated floor 532 ns · record 19409.95× above itestimate, not evidence ›
DRAM 532 ns · bandwidth-bound on B200
every declared tensor crosses HBM exactly once (8,000 GB/s, B200 datasheet)
headroom-v1: a lower bound from declared tensors and datasheet peaks. A kernel can sit well above it for good reasons.
#
Implementation
Latency
vs #1
Trust
Observed
110.3ms1.00×Reproduction-ready · Apache-2.0 · source2026-06-06
Measured exactly what you asked. The source's designated baseline implementation. Reported by source; not independently reproduced.
source mirroredApache-2.0no install recipeView source →Run detail →
Implementations
Implementation
Runtime
Best latency
Evidence
Availability
cuda_fp4_fp6_naive_n2048_k2048FlashInfer-Bench baselines
cuda
10.3ms
1.00×
Reproduction-ready
Apache-2.0 · source
Semantics
Inputs and outputs
a_fp4int8 [m, k_half]
b_fp6int8 [n, k]
cbf16 [m, n]
Axes and behavior
kconstant = 2048
mvariable
nconstant = 2048
k_halfconstant = 1024
determinismunspecified
constraintsNo mutation or aliasing
Identity
aliasgemm_fp4_fp6_n2048_k2048sha25662bff4511cce…
Sources: FlashInfer-Bench (2026-06-06) · Apache-2.0last observed 2026-06-06How records are decidedJSON