conv transposed 3D square input asymmetric kernel
4 eligible runs
conv
KernelBench level1 problem 68: conv transposed 3D square input asymmetric kernel. The computation is the reference PyTorch module's forward pass; the output shape follows the module (mirrored as each implementation's source).
Source baseline · unbeaten
11.9ms±0.06 · mean of 100
PyTorch eagerPyTorch · MIT · python
Reported evidence · last observed 2026-03-05. The source's designated baseline implementation. Reported by source; not independently reproduced.
Current records
HardwareBest knownImplementationRuns
NVIDIA H100 · env 111.9 msPyTorch eager2NVIDIA H100 · env 236.8 msPyTorch eager2Not measured on B200 for this workload. Challenges →
Source-native comparison · GPU NVIDIA H100 · Workload depth = 64 · width = 64 · height = 64 · batch_size = 16 · in_channels = 32 · fp32 · Protocol KernelBench timing scripts · mean · 2 results · last observed 2026-03-05Record history →
Estimated floor 160.3 µs · record 74.25× above itestimate, not evidence ›
DRAM 160.3 µs · bandwidth-bound on H100 SXM
every declared tensor crosses HBM exactly once (3,350 GB/s, H100 SXM datasheet)
no arithmetic formula for this family: bandwidth floor only
headroom-v1: a lower bound from declared tensors and datasheet peaks. A kernel can sit well above it for good reasons.
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Implementation
Latency
vs #1
Trust
Observed
111.9ms±0.061.00×Reported · MIT · source2026-03-05stale
Measured exactly what you asked. The source's designated baseline implementation. Reported by source; not independently reproduced.
source mirroredMITno install recipeView source →Run detail →
1=torch.compile (inductor)PyTorch11.9ms±0.061.00×Reported · MIT · source2026-03-05stale
Measured exactly what you asked; tied ranks share a number. Reported by source; not independently reproduced.
source mirroredMITno install recipeView source →Run detail →
Implementations
Implementation
Runtime
Best latency
Evidence
Availability
Semantics
Inputs and outputs
xfp32 [batch_size, in_channels, depth, width, height]
outfloat [out]
Axes and behavior
outvariable
depthvariable
widthvariable
heightvariable
batch_sizevariable
in_channelsvariable
determinismunspecified
constraintsNo mutation or aliasing
Identity
sha2560fcf68a4132a…
Sources: KernelBench baseline timings (2026-03-05) · MITlast observed 2026-03-05How records are decidedJSON