submission 844790
divyanshsinghvi · python · License unknown
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No package. Vendor the mirrored source: 5220 lines, June 9 Researcher Reciprocity License v1.0.
submission.py
curl "https://kernelindex.com/api/v1/implementations/kernelbot-qr-v2-844790?include=source"interfacepython
Compatibility
measured onNVIDIA B200
declared hardwareNVIDIA B200
architecturessm_100
dtypesfp32
Benchmark evidence
1 measurement across 1 GPU, fastest first.
Operation / workload
Hardware
Latency
Rank
Observed
Reported · How evidence levels are derived →
Source and license
sourceavailable
revision digestsha256:eb3c799c557c3778eba18837c150e7ea90f918caf91a3c2a575b044f4a1affd6
license declaredunknown
license concludedunknown
authorsdivyanshsinghvi
imported2026-08-26
Techniques
Extracted from the mirrored source by pattern, never inferred. Each row cites its line.
cluster
using Cutlass512ClusterShape = cute::Shape<cute::Int<1>, cute::Int<1>, cute::Int<1>>;fused-epilogue
using Cutlass512Epilogue = typename cutlass::epilogue::collective::CollectiveBuilder<mma
wmma::fragment<wmma::matrix_a, TILE, TILE, TILE, __half, wmma::row_major> a_frag;shared-memory
void geqrf_176_panel_smem_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width);Kernel source
submission.py5220 lines
#!POPCORN leaderboard qr_v2
#!POPCORN gpu B200
import torch
from torch.utils.cpp_extension import load_inline
from task import input_t, output_t
_PANEL = 8
_PANEL_32 = 32
_PANEL_352 = 8
_PANEL_2048 = 8
_PANEL_4096 = 8
_SUPERPANEL_512 = 32
_SUPERPANEL_1024 = 32
_SUPERPANEL_2048 = 32
_SUPERPANEL_4096 = 32
_SUPERPANEL_NS = (512, 1024, 2048)
_USE_SMEM_PANEL_512 = True
_USE_SMEM_PANEL_1024 = True
_USE_SMEM_PANEL_2048 = True
_USE_2048_PACK_BLAS_UPDATE = False
_USE_NATIVE_UPDATE_2048 = False
_USE_FUSED_512_FP32_UPDATE = False
_USE_CUTLASS_512_UPDATE = True
_USE_NATIVE_512_SUPERPANEL_DRIVER = True
_USE_NATIVE_1024_SUPERPANEL_DRIVER = True
_USE_NATIVE_2048_CUTLASS64_DRIVER = False
_USE_NATIVE_4096_DRIVER = False
_USE_NATIVE_4096_TILE_DRIVER = False
_USE_NATIVE_4096_CUTLASS64_DRIVER = False
_USE_LOW_PRECISION_UPDATE_NS = (512,)
_LOWP_MIN_TRAILING_COLS_512 = 256
_PANEL_T_NS = (176, 352)
_USE_PRECOMPUTE_U_NS = ()
_BLOCKED_NS = (32, 176, 352, 512, 1024, 2048)
_NATIVE_PANEL_NS = (32, 176, 352, 512, 1024, 2048, 4096)
CPP_SRC = r"""
#include <torch/extension.h>
#include <tuple>
void geqrf_32_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_32_warp(torch::Tensor h, torch::Tensor tau);
void geqrf_32_warp_out(torch::Tensor input, torch::Tensor h, torch::Tensor tau);
std::tuple<torch::Tensor, torch::Tensor> geqrf_32_warp_make(torch::Tensor input);
void geqrf_176_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_176_panel_smem_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width);
void geqrf_176_panel_smem_pack_t(torch::Tensor h, torch::Tensor tau, torch::Tensor v_panel, torch::Tensor t, int64_t k, int64_t width);
void geqrf_352_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_352_panel_smem_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width);
void geqrf_512_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_512_panel_smem(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_512_panel_smem_pack(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width, torch::Tensor v_panel, torch::Tensor v_block, torch::Tensor t_panel, int64_t block_k, int64_t out_col);
void geqrf_512_panel_smem_pack_h(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width, torch::Tensor v_panel, torch::Tensor v_block, torch::Tensor v_block_h, torch::Tensor t_panel, int64_t block_k, int64_t out_col);
void geqrf_1024_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_1024_panel_smem(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_2048_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_2048_panel_smem(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_2048_panel_smem_pack(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width, torch::Tensor v_panel, torch::Tensor t_panel);
void geqrf_4096_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_4096_panel_smem(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width);
void geqrf_4096_panel_smem_pack(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width, torch::Tensor v_panel, torch::Tensor t_panel);
void geqrf_176_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width);
void geqrf_352_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width);
void geqrf_512_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width);
void geqrf_1024_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width);
void geqrf_2048_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width);
void pack_v_panel(torch::Tensor h, torch::Tensor v, int64_t k, int64_t width);
void pack_v_panel_half(torch::Tensor h, torch::Tensor v, torch::Tensor vh, int64_t k, int64_t width);
void make_t_panel(torch::Tensor v, torch::Tensor tau, torch::Tensor t, int64_t width);
void merge_p8_tree_32(torch::Tensor v_block, torch::Tensor t_panels, torch::Tensor t_out);
void qr_352_superpanel32_driver(torch::Tensor h, torch::Tensor tau, torch::Tensor v_panel_storage, torch::Tensor v_block_storage, torch::Tensor t_panel_workspace, torch::Tensor t_block_workspace, torch::Tensor local_work1_storage, torch::Tensor local_work2_storage, torch::Tensor work1_storage, torch::Tensor work2_storage);
void qr_176_panel8_driver(torch::Tensor h, torch::Tensor tau, torch::Tensor v_storage, torch::Tensor t_workspace, torch::Tensor work1_storage, torch::Tensor work2_storage);
void qr_512_superpanel32_active_driver(torch::Tensor h, torch::Tensor tau, torch::Tensor v_panel_storage, torch::Tensor v_block_storage, torch::Tensor v_block_h_storage, torch::Tensor t_panel_workspace, torch::Tensor t_block_workspace, torch::Tensor local_work1_storage, torch::Tensor local_work2_storage, torch::Tensor work1_storage, torch::Tensor work2_storage, torch::Tensor work_h_storage, torch::Tensor split_v_h_storage, torch::Tensor split_work_h_storage, torch::Tensor cutlass_workspace, torch::Tensor active_problem_sizes, torch::Tensor active_ptr_a, torch::Tensor active_ptr_b, torch::Tensor active_ptr_c, torch::Tensor active_ptr_d, torch::Tensor active_lda, torch::Tensor active_ldb, torch::Tensor active_ldc, torch::Tensor active_ldd);
void qr_1024_superpanel32_driver(torch::Tensor h, torch::Tensor tau, torch::Tensor v_panel_storage, torch::Tensor v_block_storage, torch::Tensor v_block_h_storage, torch::Tensor t_panel_workspace, torch::Tensor t_block_workspace, torch::Tensor local_work1_storage, torch::Tensor local_work2_storage, torch::Tensor work1_storage, torch::Tensor work2_storage, torch::Tensor work_h_storage, torch::Tensor cutlass_workspace);
void qr_2048_superpanel64_cutlass_driver(torch::Tensor h, torch::Tensor tau, torch::Tensor v_panel_storage, torch::Tensor v_block_storage, torch::Tensor v_block_h_storage, torch::Tensor t_panel_workspace, torch::Tensor t_block_workspace, torch::Tensor local_work1_storage, torch::Tensor local_work2_storage, torch::Tensor work1_storage, torch::Tensor work2_storage, torch::Tensor work_h_storage, torch::Tensor cutlass_workspace);
void qr_4096_panel64_driver(torch::Tensor h, torch::Tensor tau, torch::Tensor v_storage, torch::Tensor t_workspace, torch::Tensor work1_storage, torch::Tensor work2_storage);
void qr_4096_superpanel32_driver(torch::Tensor h, torch::Tensor tau, torch::Tensor v_panel_storage, torch::Tensor v_block_storage, torch::Tensor t_panel_workspace, torch::Tensor t_block_workspace, torch::Tensor local_work1_storage, torch::Tensor local_work2_storage, torch::Tensor work1_storage, torch::Tensor work2_storage);
void qr_4096_superpanel64_cutlass_driver(torch::Tensor h, torch::Tensor tau, torch::Tensor v_panel_storage, torch::Tensor v_block_storage, torch::Tensor v_block_h_storage, torch::Tensor t_panel_workspace, torch::Tensor t_block_workspace, torch::Tensor local_work1_storage, torch::Tensor local_work2_storage, torch::Tensor work1_storage, torch::Tensor work2_storage, torch::Tensor work_h_storage, torch::Tensor cutlass_workspace);
int64_t detect_zero_tail_rank_512(torch::Tensor data);
int64_t detect_clustered_effective_cols_512(torch::Tensor data, double rel_threshold);
int64_t detect_nearrank_duplicate_rank_1024(torch::Tensor data, double rel_threshold);
void finalize_nearrank_tail_1024(torch::Tensor h, torch::Tensor tau, int64_t rank);
void update_512_w16_fused(torch::Tensor h, torch::Tensor v, torch::Tensor t, int64_t k, int64_t next_col);
void update_512_w16_hacc(torch::Tensor h, torch::Tensor v, torch::Tensor work, int64_t k, int64_t next_col);
void update_512_w16_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col);
void update_512_w32_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col);
void update_1024_w16_hacc(torch::Tensor h, torch::Tensor v, torch::Tensor work, int64_t k, int64_t next_col);
void update_1024_w32_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col);
void update_2048_w64_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col);
void update_4096_w64_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col);
void update_2048_w4(torch::Tensor h, torch::Tensor v, torch::Tensor t, int64_t k, int64_t next_col);
void update_2048_w4_tile8(torch::Tensor h, torch::Tensor v, torch::Tensor t, int64_t k, int64_t next_col);
void update_2048_w8_tile8(torch::Tensor h, torch::Tensor v, torch::Tensor t, int64_t k, int64_t next_col);
"""
CUDA_SRC = r"""
#include <torch/extension.h>
#include <ATen/ops/baddbmm.h>
#include <ATen/ops/bmm.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <mma.h>
// #if __has_include(<cutlass/cutlass.h>) && __has_include(<cute/tensor.hpp>)
#define QRV2_HAS_CUTLASS 1
#include <cutlass/cutlass.h>
#include <cutlass/arch/arch.h>
#include <cutlass/epilogue/collective/collective_builder.hpp>
#include <cutlass/epilogue/collective/default_epilogue.hpp>
#include <cutlass/epilogue/thread/linear_combination.h>
#include <cutlass/gemm/collective/collective_builder.hpp>
#include <cutlass/gemm/device/gemm_grouped.h>
#include <cutlass/gemm/device/gemm_universal_adapter.h>
#include <cutlass/gemm/dispatch_policy.hpp>
#include <cutlass/gemm/gemm.h>
#include <cutlass/gemm/kernel/default_gemm_grouped.h>
#include <cutlass/gemm/kernel/gemm_grouped.h>
#include <cutlass/gemm/kernel/gemm_universal.hpp>
#include <cutlass/gemm/kernel/tile_scheduler.hpp>
#include <cutlass/half.h>
#include <cutlass/layout/matrix.h>
#include <cutlass/util/packed_stride.hpp>
#include <cute/tensor.hpp>
// #else
// #define QRV2_HAS_CUTLASS 0
// #endif
#include <cmath>
#include <stdexcept>
#include <string>
namespace {
using namespace nvcuda;
constexpr int PANEL = 64;
constexpr int MAX_PANEL = 128;
constexpr int THREADS = 256;
constexpr int REDUCE_WARPS = (THREADS + 31) / 32;
constexpr int THREADS_176_PANEL = 256;
// #if QRV2_HAS_CUTLASS
using Cutlass512ElementA = cutlass::half_t;
using Cutlass512ElementB = cutlass::half_t;
using Cutlass512ElementC = float;
using Cutlass512Accumulator = float;
using Cutlass512ProblemShape = cute::Shape<int, int, int, int>;
using Cutlass512TileShape = cute::Shape<cute::Int<64>, cute::Int<64>, cute::Int<16>>;
using Cutlass512ClusterShape = cute::Shape<cute::Int<1>, cute::Int<1>, cute::Int<1>>;
using Cutlass512Mainloop = typename cutlass::gemm::collective::CollectiveBuilder<
cutlass::arch::Sm100,
cutlass::arch::OpClassTensorOp,
Cutlass512ElementA,
cutlass::layout::RowMajor,
8,
Cutlass512ElementB,
cutlass::layout::RowMajor,
8,
Cutlass512Accumulator,
Cutlass512TileShape,
Cutlass512ClusterShape,
cutlass::gemm::collective::StageCount<2>,
cutlass::gemm::collective::KernelScheduleAuto>::CollectiveOp;
using Cutlass512Epilogue = typename cutlass::epilogue::collective::CollectiveBuilder<
cutlass::arch::Sm100,
cutlass::arch::OpClassTensorOp,
Cutlass512TileShape,
Cutlass512ClusterShape,
cutlass::epilogue::collective::EpilogueTileAuto,
Cutlass512Accumulator,
Cutlass512Accumulator,
Cutlass512ElementC,
cutlass::layout::RowMajor,
4,
Cutlass512ElementC,
cutlass::layout::RowMajor,
4,
cutlass::epilogue::collective::EpilogueScheduleAuto>::CollectiveOp;
using Cutlass512Kernel = cutlass::gemm::kernel::GemmUniversal<
Cutlass512ProblemShape,
Cutlass512Mainloop,
Cutlass512Epilogue>;
using Cutlass512Gemm = cutlass::gemm::device::GemmUniversalAdapter<Cutlass512Kernel>;
using Cutlass512GroupedEpilogue = cutlass::epilogue::thread::LinearCombination<
Cutlass512ElementC,
1,
Cutlass512Accumulator,
Cutlass512Accumulator>;
using Cutlass512GroupedKernel = typename cutlass::gemm::kernel::DefaultGemmGrouped<
Cutlass512ElementA,
cutlass::layout::RowMajor,
cutlass::ComplexTransform::kNone,
8,
Cutlass512ElementB,
cutlass::layout::RowMajor,
cutlass::ComplexTransform::kNone,
8,
Cutlass512ElementC,
cutlass::layout::RowMajor,
Cutlass512Accumulator,
cutlass::arch::OpClassTensorOp,
cutlass::arch::Sm80,
cutlass::gemm::GemmShape<64, 64, 64>,
cutlass::gemm::GemmShape<32, 32, 32>,
cutlass::gemm::GemmShape<16, 8, 16>,
Cutlass512GroupedEpilogue,
cutlass::gemm::threadblock::GemmBatchedIdentityThreadblockSwizzle,
4,
cutlass::gemm::kernel::GroupScheduleMode::kDeviceOnly>::GemmKernel;
using Cutlass512GroupedGemm = cutlass::gemm::device::GemmGrouped<Cutlass512GroupedKernel>;
// #endif
inline void check_cuda(cudaError_t status, const char* what) {
if (status != cudaSuccess) {
throw std::runtime_error(std::string(what) + ": " + cudaGetErrorString(status));
}
}
__device__ float warp_sum_f32(float value) {
#pragma unroll
for (int offset = 16; offset > 0; offset >>= 1) {
value += __shfl_down_sync(0xffffffffu, value, offset);
}
return value;
}
__device__ float block_sum_f32(float value, float* scratch) {
const int tid = threadIdx.x;
const int lane = tid & 31;
const int warp = tid >> 5;
value = warp_sum_f32(value);
if (lane == 0) {
scratch[warp] = value;
}
__syncthreads();
value = 0.0f;
const int num_warps = (blockDim.x + 31) >> 5;
if (warp == 0 && lane < num_warps) {
value = scratch[lane];
}
value = warp_sum_f32(value);
if (tid == 0) {
scratch[0] = value;
}
__syncthreads();
return scratch[0];
}
__device__ float block_sum_tid0_f32(float value, float* scratch) {
const int tid = threadIdx.x;
const int lane = tid & 31;
const int warp = tid >> 5;
value = warp_sum_f32(value);
if (lane == 0) {
scratch[warp] = value;
}
__syncthreads();
value = 0.0f;
const int num_warps = (blockDim.x + 31) >> 5;
if (warp == 0 && lane < num_warps) {
value = scratch[lane];
}
value = warp_sum_f32(value);
return value;
}
__device__ int warp_or_i32(int value) {
#pragma unroll
for (int offset = 16; offset > 0; offset >>= 1) {
value |= __shfl_down_sync(0xffffffffu, value, offset);
}
return value;
}
__device__ int block_or_tid0_i32(int value, int* scratch) {
const int tid = threadIdx.x;
const int lane = tid & 31;
const int warp = tid >> 5;
value = warp_or_i32(value);
if (lane == 0) {
scratch[warp] = value;
}
__syncthreads();
value = 0;
const int num_warps = (blockDim.x + 31) >> 5;
if (warp == 0 && lane < num_warps) {
value = scratch[lane];
}
value = warp_or_i32(value);
return value;
}
__device__ float warp_max_f32(float value) {
#pragma unroll
for (int offset = 16; offset > 0; offset >>= 1) {
value = fmaxf(value, __shfl_down_sync(0xffffffffu, value, offset));
}
return value;
}
__device__ float block_max_tid0_f32(float value, float* scratch) {
const int tid = threadIdx.x;
const int lane = tid & 31;
const int warp = tid >> 5;
value = warp_max_f32(value);
if (lane == 0) {
scratch[warp] = value;
}
__syncthreads();
value = 0.0f;
const int num_warps = (blockDim.x + 31) >> 5;
if (warp == 0 && lane < num_warps) {
value = scratch[lane];
}
value = warp_max_f32(value);
return value;
}
__device__ int warp_max_i32(int value) {
#pragma unroll
for (int offset = 16; offset > 0; offset >>= 1) {
const int other = __shfl_down_sync(0xffffffffu, value, offset);
value = value > other ? value : other;
}
return value;
}
__device__ int block_max_tid0_i32(int value, int* scratch) {
const int tid = threadIdx.x;
const int lane = tid & 31;
const int warp = tid >> 5;
value = warp_max_i32(value);
if (lane == 0) {
scratch[warp] = value;
}
__syncthreads();
value = -1;
const int num_warps = (blockDim.x + 31) >> 5;
if (warp == 0 && lane < num_warps) {
value = scratch[lane];
}
value = warp_max_i32(value);
return value;
}
__global__ void detect_zero_tail_rank_512_kernel(const float* __restrict__ data,
int batch,
int* __restrict__ last_nonzero_col) {
constexpr int N = 512;
const int col = blockIdx.x;
const int tid = threadIdx.x;
__shared__ int scratch[REDUCE_WARPS];
if (col >= N) {
return;
}
int any = 0;
const int total_rows = batch * N;
for (int idx = tid; idx < total_rows; idx += blockDim.x) {
const int b = idx / N;
const int row = idx - b * N;
const float value = data[(static_cast<long long>(b) * N + row) * N + col];
any |= (value != 0.0f);
}
const int col_has_data = block_or_tid0_i32(any, scratch);
if (tid == 0 && col_has_data) {
atomicMax(last_nonzero_col, col);
}
}
__global__ void classify_zero_tail_active_cols_512_kernel(const float* __restrict__ data,
int batch,
int* __restrict__ active_cols) {
constexpr int N = 512;
const int b = blockIdx.x;
const int tid = threadIdx.x;
__shared__ int scratch[REDUCE_WARPS];
if (b >= batch) {
return;
}
int local_last = -1;
const float* matrix = data + static_cast<long long>(b) * N * N;
for (int idx = tid; idx < N * N; idx += blockDim.x) {
const float value = matrix[idx];
if (value != 0.0f) {
const int col = idx - (idx / N) * N;
local_last = local_last > col ? local_last : col;
}
}
const int last = block_max_tid0_i32(local_last, scratch);
if (tid == 0) {
active_cols[b] = last + 1;
}
}
__global__ void finalize_zero_tail_active_cols_512_kernel(float* __restrict__ h,
float* __restrict__ tau,
const int* __restrict__ active_cols,
int batch) {
constexpr int N = 512;
const int b = blockIdx.x;
const int tid = threadIdx.x;
if (b >= batch) {
return;
}
const int active = active_cols[b];
if (active >= N) {
return;
}
float* a = h + static_cast<long long>(b) * N * N;
float* tb = tau + static_cast<long long>(b) * N;
for (int idx = tid; idx < N * (N - active); idx += blockDim.x) {
const int row = idx / (N - active);
const int col = active + idx - row * (N - active);
a[row * N + col] = 0.0f;
}
for (int col = active + tid; col < N; col += blockDim.x) {
tb[col] = 0.0f;
}
}
template <int N>
__global__ void column_max_kernel(const float* __restrict__ data,
int batch,
float* __restrict__ col_max) {
const int col = blockIdx.x;
const int tid = threadIdx.x;
__shared__ float scratch[REDUCE_WARPS];
if (col >= N) {
return;
}
float local = 0.0f;
const int total_rows = batch * N;
for (int idx = tid; idx < total_rows; idx += blockDim.x) {
const int b = idx / N;
const int row = idx - b * N;
const float value = fabsf(data[(static_cast<long long>(b) * N + row) * N + col]);
local = fmaxf(local, value);
}
const float mx = block_max_tid0_f32(local, scratch);
if (tid == 0) {
col_max[col] = mx;
}
}
__global__ void clustered_effective_cols_512_kernel(const float* __restrict__ col_max,
float rel_threshold,
int* __restrict__ effective_cols) {
constexpr int N = 512;
const int tid = threadIdx.x;
__shared__ float f_scratch[REDUCE_WARPS];
__shared__ int i_scratch[REDUCE_WARPS];
float local_scale = 0.0f;
for (int col = tid; col < N; col += blockDim.x) {
local_scale = fmaxf(local_scale, col_max[col]);
}
const float scale = block_max_tid0_f32(local_scale, f_scratch);
const float limit = scale * rel_threshold;
int local_last = -1;
if (scale > 0.0f) {
for (int col = tid; col < N; col += blockDim.x) {
if (col_max[col] > limit) {
local_last = local_last > col ? local_last : col;
}
}
}
const int last = block_max_tid0_i32(local_last, i_scratch);
if (tid == 0) {
if (scale == 0.0f) {
effective_cols[0] = 0;
} else {
const int eff = ((last + 1 + 7) / 8) * 8;
effective_cols[0] = (eff >= N) ? -1 : eff;
}
}
}
__global__ void detect_nearrank_duplicate_rank_1024_kernel(const float* __restrict__ data,
int batch,
float rel_threshold,
int* __restrict__ rank_out) {
constexpr int N = 1024;
const int candidate = (N / 2) + blockIdx.x;
const int tid = threadIdx.x;
__shared__ float base_scratch[REDUCE_WARPS];
__shared__ float diff_scratch[REDUCE_WARPS];
if (candidate >= N) {
return;
}
float base_local = 0.0f;
float diff_local = 0.0f;
const int total_rows = batch * N;
for (int idx = tid; idx < total_rows; idx += blockDim.x) {
const int b = idx / N;
const int row = idx - b * N;
const long long base_offset = (static_cast<long long>(b) * N + row) * N;
const float head = data[base_offset];
const float tail = data[base_offset + candidate];
base_local = fmaxf(base_local, fabsf(head));
diff_local = fmaxf(diff_local, fabsf(tail - head));
}
const float base = block_max_tid0_f32(base_local, base_scratch);
const float diff = block_max_tid0_f32(diff_local, diff_scratch);
if (tid == 0 && base > 0.0f && diff < base * rel_threshold) {
atomicMin(rank_out, candidate);
}
}
__global__ void finalize_nearrank_tail_1024_kernel(float* __restrict__ h,
float* __restrict__ tau,
int batch,
int rank) {
constexpr int N = 1024;
const int j = blockIdx.x;
const int b = blockIdx.y;
const int tid = threadIdx.x;
const int tail = N - rank;
if (b >= batch || j >= tail) {
return;
}
float* a = h + static_cast<long long>(b) * N * N;
if (tid == 0) {
tau[static_cast<long long>(b) * N + rank + j] = 0.0f;
}
for (int row = tid; row < N; row += blockDim.x) {
float value = 0.0f;
if (row <= j) {
value = a[row * N + j];
}
a[row * N + rank + j] = value;
}
}
template <int N, bool BUILD_T>
__global__ void __launch_bounds__(THREADS, 2) geqrf_panel_kernel(float* __restrict__ h,
float* __restrict__ tau,
float* __restrict__ t_out,
int batch,
int k,
int width) {
const int b = blockIdx.x;
const int tid = threadIdx.x;
if (b >= batch) {
return;
}
__shared__ float scratch[REDUCE_WARPS];
__shared__ float beta_s;
__shared__ float tau_s;
__shared__ float inv_s;
__shared__ float update_s;
float* a = h + static_cast<long long>(b) * N * N;
float* t = tau + static_cast<long long>(b) * N;
for (int jj = 0; jj < width; ++jj) {
const int col = k + jj;
float tail_local = 0.0f;
for (int row = col + 1 + tid; row < N; row += blockDim.x) {
const float x = a[row * N + col];
tail_local += x * x;
}
const float tail_norm_sq = block_sum_tid0_f32(tail_local, scratch);
if (tid == 0) {
const float alpha = a[col * N + col];
if (tail_norm_sq == 0.0f) {
beta_s = alpha;
tau_s = 0.0f;
inv_s = 0.0f;
} else {
const float norm = sqrtf(alpha * alpha + tail_norm_sq);
const float beta = (alpha >= 0.0f) ? -norm : norm;
beta_s = beta;
tau_s = (beta - alpha) / beta;
inv_s = 1.0f / (alpha - beta);
}
t[col] = tau_s;
}
__syncthreads();
if (tau_s != 0.0f) {
for (int row = col + 1 + tid; row < N; row += blockDim.x) {
a[row * N + col] *= inv_s;
}
}
__syncthreads();
if (tau_s != 0.0f) {
for (int j2 = jj + 1; j2 < width; ++j2) {
const int update_col = k + j2;
float dot_local = (tid == 0) ? a[col * N + update_col] : 0.0f;
for (int row = col + 1 + tid; row < N; row += blockDim.x) {
dot_local += a[row * N + col] * a[row * N + update_col];
}
const float dot = block_sum_tid0_f32(dot_local, scratch);
if (tid == 0) {
update_s = tau_s * static_cast<float>(dot);
a[col * N + update_col] -= update_s;
}
__syncthreads();
for (int row = col + 1 + tid; row < N; row += blockDim.x) {
a[row * N + update_col] -= a[row * N + col] * update_s;
}
}
__syncthreads();
}
if (tid == 0) {
a[col * N + col] = beta_s;
}
__syncthreads();
}
if constexpr (BUILD_T) {
__shared__ float t_col[MAX_PANEL];
__shared__ float tau_j_s;
float* tb = t_out + static_cast<long long>(b) * width * width;
const int rows = N - k;
for (int idx = tid; idx < width * width; idx += blockDim.x) {
tb[idx] = 0.0f;
}
__syncthreads();
for (int j = 0; j < width; ++j) {
if (tid == 0) {
tau_j_s = t[k + j];
}
__syncthreads();
if (j > 0 && tau_j_s != 0.0f) {
for (int i = 0; i < j; ++i) {
float local = 0.0f;
for (int row = j + tid; row < rows; row += blockDim.x) {
float vi = 0.0f;
if (row == i) {
vi = 1.0f;
} else if (row > i) {
vi = a[(k + row) * N + (k + i)];
}
float vj = 0.0f;
if (row == j) {
vj = 1.0f;
} else if (row > j) {
vj = a[(k + row) * N + (k + j)];
}
local += vi * vj;
}
const float dot = block_sum_f32(local, scratch);
if (tid == 0) {
t_col[i] = -tau_j_s * static_cast<float>(dot);
}
}
__syncthreads();
for (int i = tid; i < j; i += blockDim.x) {
float acc = 0.0f;
for (int q = 0; q < j; ++q) {
acc += tb[i * width + q] * t_col[q];
}
tb[i * width + j] = acc;
}
__syncthreads();
}
if (tid == 0) {
tb[j * width + j] = tau_j_s;
}
__syncthreads();
}
}
}
__global__ void geqrf_32_warp_kernel(const float* __restrict__ input,
float* __restrict__ h,
float* __restrict__ tau,
int batch) {
constexpr int N = 32;
constexpr int WARPS_PER_BLOCK = 8;
const int lane = threadIdx.x & 31;
const int warp_in_block = threadIdx.x >> 5;
const int b = blockIdx.x * WARPS_PER_BLOCK + warp_in_block;
if (b >= batch) {
return;
}
float* a = h + static_cast<long long>(b) * N * N;
float* t = tau + static_cast<long long>(b) * N;
const float* src = input == nullptr ? a : input + static_cast<long long>(b) * N * N;
float row_values[N];
#pragma unroll
for (int j = 0; j < N; ++j) {
row_values[j] = src[lane * N + j];
}
#pragma unroll
for (int col = 0; col < N; ++col) {
const float tail_local = lane > col ? row_values[col] * row_values[col] : 0.0f;
const float tail_norm_sq = warp_sum_f32(tail_local);
const float alpha = __shfl_sync(0xffffffffu, row_values[col], col);
float beta = 0.0f;
float tau_col = 0.0f;
float inv = 0.0f;
if (lane == 0) {
if (tail_norm_sq == 0.0f) {
beta = alpha;
tau_col = 0.0f;
inv = 0.0f;
} else {
const float norm = sqrtf(alpha * alpha + tail_norm_sq);
beta = (alpha >= 0.0f) ? -norm : norm;
tau_col = (beta - alpha) / beta;
inv = 1.0f / (alpha - beta);
}
t[col] = tau_col;
}
beta = __shfl_sync(0xffffffffu, beta, 0);
tau_col = __shfl_sync(0xffffffffu, tau_col, 0);
inv = __shfl_sync(0xffffffffu, inv, 0);
if (tau_col != 0.0f && lane > col) {
row_values[col] *= inv;
}
if (tau_col != 0.0f) {
#pragma unroll
for (int update_col = col + 1; update_col < N; ++update_col) {
float dot_local = 0.0f;
if (lane == col) {
dot_local = row_values[update_col];
} else if (lane > col) {
dot_local = row_values[col] * row_values[update_col];
}
const float dot = warp_sum_f32(dot_local);
float update = 0.0f;
if (lane == 0) {
update = tau_col * dot;
}
update = __shfl_sync(0xffffffffu, update, 0);
if (lane == col) {
row_values[update_col] -= update;
} else if (lane > col) {
row_values[update_col] -= row_values[col] * update;
}
}
}
if (lane == col) {
row_values[col] = beta;
}
}
#pragma unroll
for (int j = 0; j < N; ++j) {
a[lane * N + j] = row_values[j];
}
}
__global__ void __launch_bounds__(THREADS) geqrf_512_panel_smem_kernel(float* __restrict__ h,
float* __restrict__ tau,
float* __restrict__ v_panel_out,
float* __restrict__ v_block_out,
__half* __restrict__ v_block_half_out,
float* __restrict__ t_panel_out,
int batch,
int k,
int width,
int block_k,
int block_width,
int out_col) {
constexpr int N = 512;
constexpr int W = 8;
constexpr int PANEL_LD = N + 1;
const int b = blockIdx.x;
const int tid = threadIdx.x;
if (b >= batch) {
return;
}
__shared__ float panel[PANEL_LD * W];
__shared__ float scratch[REDUCE_WARPS];
__shared__ float beta_s;
__shared__ float tau_s;
__shared__ float inv_s;
__shared__ float update_s;
__shared__ float t_col[W];
__shared__ float t_scratch[W * REDUCE_WARPS];
__shared__ float tau_j_s;
float* a = h + static_cast<long long>(b) * N * N;
float* t = tau + static_cast<long long>(b) * N;
const int rows = N - k;
float* vp = v_panel_out == nullptr ? nullptr : v_panel_out + static_cast<long long>(b) * rows * width;
const int block_rows = N - block_k;
float* vb = v_block_out == nullptr ? nullptr : v_block_out + static_cast<long long>(b) * block_rows * block_width;
__half* vbh = v_block_half_out == nullptr ? nullptr : v_block_half_out + static_cast<long long>(b) * block_rows * block_width;
float* tb = t_panel_out == nullptr ? nullptr : t_panel_out + static_cast<long long>(b) * width * width;
for (int idx = tid; idx < rows * width; idx += blockDim.x) {
const int row = idx / width;
const int col = idx - row * width;
panel[col * PANEL_LD + row] = a[(k + row) * N + (k + col)];
}
__syncthreads();
for (int jj = 0; jj < width; ++jj) {
float tail_local = 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
const float x = panel[jj * PANEL_LD + row];
tail_local += x * x;
}
const float tail_norm_sq = block_sum_tid0_f32(tail_local, scratch);
if (tid == 0) {
const float alpha = panel[jj * PANEL_LD + jj];
if (tail_norm_sq == 0.0f) {
beta_s = alpha;
tau_s = 0.0f;
inv_s = 0.0f;
} else {
const float norm = sqrtf(alpha * alpha + tail_norm_sq);
const float beta = (alpha >= 0.0f) ? -norm : norm;
beta_s = beta;
tau_s = (beta - alpha) / beta;
inv_s = 1.0f / (alpha - beta);
}
t[k + jj] = tau_s;
}
__syncthreads();
if (tau_s != 0.0f) {
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[jj * PANEL_LD + row] *= inv_s;
}
}
__syncthreads();
if (tau_s != 0.0f) {
for (int j2 = jj + 1; j2 < width; ++j2) {
float dot_local = (tid == 0) ? panel[j2 * PANEL_LD + jj] : 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
dot_local += panel[jj * PANEL_LD + row] * panel[j2 * PANEL_LD + row];
}
const float dot = block_sum_tid0_f32(dot_local, scratch);
if (tid == 0) {
update_s = tau_s * static_cast<float>(dot);
panel[j2 * PANEL_LD + jj] -= update_s;
}
__syncthreads();
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[j2 * PANEL_LD + row] -= panel[jj * PANEL_LD + row] * update_s;
}
}
__syncthreads();
}
if (tid == 0) {
panel[jj * PANEL_LD + jj] = beta_s;
}
__syncthreads();
}
for (int idx = tid; idx < rows * width; idx += blockDim.x) {
const int row = idx / width;
const int col = idx - row * width;
a[(k + row) * N + (k + col)] = panel[col * PANEL_LD + row];
}
if (vp != nullptr) {
for (int idx = tid; idx < rows * width; idx += blockDim.x) {
const int row = idx / width;
const int col = idx - row * width;
float value = 0.0f;
if (row == col) {
value = 1.0f;
} else if (row > col) {
value = panel[col * PANEL_LD + row];
}
vp[row * width + col] = value;
}
}
if (vb != nullptr) {
for (int idx = tid; idx < block_rows * width; idx += blockDim.x) {
const int vrow = idx / width;
const int col = idx - vrow * width;
const int local_row = vrow - out_col;
float value = 0.0f;
if (local_row == col) {
value = 1.0f;
} else if (local_row > col && local_row < rows) {
value = panel[col * PANEL_LD + local_row];
}
vb[vrow * block_width + (out_col + col)] = value;
if (vbh != nullptr) {
vbh[vrow * block_width + (out_col + col)] = __float2half(value);
}
}
}
if (tb != nullptr) {
for (int idx = tid; idx < width * width; idx += blockDim.x) {
tb[idx] = 0.0f;
}
__syncthreads();
for (int j = 0; j < width; ++j) {
if (tid == 0) {
tau_j_s = t[k + j];
}
__syncthreads();
if (j > 0 && tau_j_s != 0.0f) {
for (int i = 0; i < j; ++i) {
float local = 0.0f;
for (int row = j + tid; row < rows; row += blockDim.x) {
float vi = 0.0f;
if (row == i) {
vi = 1.0f;
} else if (row > i) {
vi = panel[i * PANEL_LD + row];
}
float vj = 0.0f;
if (row == j) {
vj = 1.0f;
} else if (row > j) {
vj = panel[j * PANEL_LD + row];
}
local += vi * vj;
}
const float dot = block_sum_tid0_f32(local, t_scratch + i * REDUCE_WARPS);
if (tid == 0) {
t_col[i] = -tau_j_s * static_cast<float>(dot);
}
}
__syncthreads();
for (int i = tid; i < j; i += blockDim.x) {
float acc = 0.0f;
for (int q = 0; q < j; ++q) {
acc += tb[i * width + q] * t_col[q];
}
tb[i * width + j] = acc;
}
__syncthreads();
}
if (tid == 0) {
tb[j * width + j] = tau_j_s;
}
__syncthreads();
}
}
}
template <int N, int W>
__global__ void __launch_bounds__(THREADS, 2) geqrf_panel_smem_basic_kernel(float* __restrict__ h,
float* __restrict__ tau,
float* __restrict__ v_panel_out,
float* __restrict__ t_panel_out,
int batch,
int k,
int width) {
const int b = blockIdx.x;
const int tid = threadIdx.x;
if (b >= batch) {
return;
}
__shared__ float panel[N * W];
__shared__ float scratch[REDUCE_WARPS];
__shared__ float beta_s;
__shared__ float tau_s;
__shared__ float inv_s;
__shared__ float update_s;
__shared__ float t_col[W];
__shared__ float t_scratch[W * REDUCE_WARPS];
__shared__ float tau_j_s;
float* a = h + static_cast<long long>(b) * N * N;
float* t = tau + static_cast<long long>(b) * N;
const int rows = N - k;
float* vp = v_panel_out == nullptr ? nullptr : v_panel_out + static_cast<long long>(b) * rows * width;
float* tb = t_panel_out == nullptr ? nullptr : t_panel_out + static_cast<long long>(b) * width * width;
for (int idx = tid; idx < rows * width; idx += blockDim.x) {
const int row = idx / width;
const int col = idx - row * width;
panel[col * N + row] = a[(k + row) * N + (k + col)];
}
__syncthreads();
for (int jj = 0; jj < width; ++jj) {
float tail_local = 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
const float x = panel[jj * N + row];
tail_local += x * x;
}
const float tail_norm_sq = block_sum_tid0_f32(tail_local, scratch);
if (tid == 0) {
const float alpha = panel[jj * N + jj];
if (tail_norm_sq == 0.0f) {
beta_s = alpha;
tau_s = 0.0f;
inv_s = 0.0f;
} else {
const float norm = sqrtf(alpha * alpha + tail_norm_sq);
const float beta = (alpha >= 0.0f) ? -norm : norm;
beta_s = beta;
tau_s = (beta - alpha) / beta;
inv_s = 1.0f / (alpha - beta);
}
t[k + jj] = tau_s;
}
__syncthreads();
if (tau_s != 0.0f) {
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[jj * N + row] *= inv_s;
}
}
__syncthreads();
if (tau_s != 0.0f) {
for (int j2 = jj + 1; j2 < width; ++j2) {
float dot_local = (tid == 0) ? panel[j2 * N + jj] : 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
dot_local += panel[jj * N + row] * panel[j2 * N + row];
}
const float dot = block_sum_tid0_f32(dot_local, scratch);
if (tid == 0) {
update_s = tau_s * static_cast<float>(dot);
panel[j2 * N + jj] -= update_s;
}
__syncthreads();
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[j2 * N + row] -= panel[jj * N + row] * update_s;
}
}
__syncthreads();
}
if (tid == 0) {
panel[jj * N + jj] = beta_s;
}
__syncthreads();
}
for (int idx = tid; idx < rows * width; idx += blockDim.x) {
const int row = idx / width;
const int col = idx - row * width;
a[(k + row) * N + (k + col)] = panel[col * N + row];
}
if (vp != nullptr) {
for (int idx = tid; idx < rows * width; idx += blockDim.x) {
const int row = idx / width;
const int col = idx - row * width;
float value = 0.0f;
if (row == col) {
value = 1.0f;
} else if (row > col) {
value = panel[col * N + row];
}
vp[row * width + col] = value;
}
}
if (tb != nullptr) {
for (int idx = tid; idx < width * width; idx += blockDim.x) {
tb[idx] = 0.0f;
}
__syncthreads();
for (int j = 0; j < width; ++j) {
if (tid == 0) {
tau_j_s = t[k + j];
}
__syncthreads();
if (j > 0 && tau_j_s != 0.0f) {
for (int i = 0; i < j; ++i) {
float local = 0.0f;
for (int row = j + tid; row < rows; row += blockDim.x) {
float vi = 0.0f;
if (row == i) {
vi = 1.0f;
} else if (row > i) {
vi = panel[i * N + row];
}
float vj = 0.0f;
if (row == j) {
vj = 1.0f;
} else if (row > j) {
vj = panel[j * N + row];
}
local += vi * vj;
}
const float dot = block_sum_tid0_f32(local, t_scratch + i * REDUCE_WARPS);
if (tid == 0) {
t_col[i] = -tau_j_s * static_cast<float>(dot);
}
}
__syncthreads();
for (int i = tid; i < j; i += blockDim.x) {
float acc = 0.0f;
for (int q = 0; q < j; ++q) {
acc += tb[i * width + q] * t_col[q];
}
tb[i * width + j] = acc;
}
__syncthreads();
}
if (tid == 0) {
tb[j * width + j] = tau_j_s;
}
__syncthreads();
}
}
}
__global__ void __launch_bounds__(THREADS_176_PANEL, 2) geqrf_176_panel_smem_t_kernel(float* __restrict__ h,
float* __restrict__ tau,
float* __restrict__ v_panel_out,
float* __restrict__ t_panel_out,
int batch,
int k) {
constexpr int N = 176;
constexpr int W = 8;
const int b = blockIdx.x;
const int tid = threadIdx.x;
if (b >= batch) {
return;
}
__shared__ float panel[N * W];
__shared__ float scratch[REDUCE_WARPS];
__shared__ float beta_s;
__shared__ float tau_s;
__shared__ float inv_s;
__shared__ float update_s;
__shared__ float t_col[W];
__shared__ float t_scratch[W * REDUCE_WARPS];
__shared__ float tau_j_s;
float* a = h + static_cast<long long>(b) * N * N;
float* t = tau + static_cast<long long>(b) * N;
float* tb = t_panel_out + static_cast<long long>(b) * W * W;
const int rows = N - k;
for (int idx = tid; idx < rows * W; idx += blockDim.x) {
const int row = idx / W;
const int col = idx - row * W;
panel[col * N + row] = a[(k + row) * N + (k + col)];
}
__syncthreads();
#pragma unroll
for (int jj = 0; jj < W; ++jj) {
float tail_local = 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
const float x = panel[jj * N + row];
tail_local += x * x;
}
const float tail_norm_sq = block_sum_tid0_f32(tail_local, scratch);
if (tid == 0) {
const float alpha = panel[jj * N + jj];
if (tail_norm_sq == 0.0f) {
beta_s = alpha;
tau_s = 0.0f;
inv_s = 0.0f;
} else {
const float norm = sqrtf(alpha * alpha + tail_norm_sq);
const float beta = (alpha >= 0.0f) ? -norm : norm;
beta_s = beta;
tau_s = (beta - alpha) / beta;
inv_s = 1.0f / (alpha - beta);
}
t[k + jj] = tau_s;
}
__syncthreads();
if (tau_s != 0.0f) {
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[jj * N + row] *= inv_s;
}
}
__syncthreads();
if (tau_s != 0.0f) {
#pragma unroll
for (int j2 = jj + 1; j2 < W; ++j2) {
float dot_local = (tid == 0) ? panel[j2 * N + jj] : 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
dot_local += panel[jj * N + row] * panel[j2 * N + row];
}
const float dot = block_sum_tid0_f32(dot_local, scratch);
if (tid == 0) {
update_s = tau_s * static_cast<float>(dot);
panel[j2 * N + jj] -= update_s;
}
__syncthreads();
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[j2 * N + row] -= panel[jj * N + row] * update_s;
}
}
__syncthreads();
}
if (tid == 0) {
panel[jj * N + jj] = beta_s;
}
__syncthreads();
}
for (int idx = tid; idx < rows * W; idx += blockDim.x) {
const int row = idx / W;
const int col = idx - row * W;
a[(k + row) * N + (k + col)] = panel[col * N + row];
}
if (v_panel_out != nullptr) {
for (int idx = tid; idx < rows * W; idx += blockDim.x) {
const int row = idx / W;
const int col = idx - row * W;
float value = 0.0f;
if (row == col) {
value = 1.0f;
} else if (row > col) {
value = panel[col * N + row];
}
v_panel_out[(static_cast<long long>(b) * rows + row) * W + col] = value;
}
}
for (int idx = tid; idx < W * W; idx += blockDim.x) {
tb[idx] = 0.0f;
}
__syncthreads();
#pragma unroll
for (int j = 0; j < W; ++j) {
if (tid == 0) {
tau_j_s = t[k + j];
}
__syncthreads();
if (j > 0 && tau_j_s != 0.0f) {
#pragma unroll
for (int i = 0; i < j; ++i) {
float local = 0.0f;
for (int row = j + tid; row < rows; row += blockDim.x) {
const float vi = panel[i * N + row];
float vj = 0.0f;
if (row == j) {
vj = 1.0f;
} else if (row > j) {
vj = panel[j * N + row];
}
local += vi * vj;
}
const float dot = block_sum_tid0_f32(local, t_scratch + i * REDUCE_WARPS);
if (tid == 0) {
t_col[i] = -tau_j_s * static_cast<float>(dot);
}
}
__syncthreads();
for (int i = tid; i < j; i += blockDim.x) {
float acc = 0.0f;
#pragma unroll
for (int q = 0; q < j; ++q) {
acc += tb[i * W + q] * t_col[q];
}
tb[i * W + j] = acc;
}
__syncthreads();
}
if (tid == 0) {
tb[j * W + j] = tau_j_s;
}
__syncthreads();
}
}
__global__ void __launch_bounds__(THREADS, 2) geqrf_352_panel_smem_t_kernel(float* __restrict__ h,
float* __restrict__ tau,
float* __restrict__ t_panel_out,
int batch,
int k) {
constexpr int N = 352;
constexpr int W = 8;
const int b = blockIdx.x;
const int tid = threadIdx.x;
if (b >= batch) {
return;
}
__shared__ float panel[N * W];
__shared__ float scratch[REDUCE_WARPS];
__shared__ float beta_s;
__shared__ float tau_s;
__shared__ float inv_s;
__shared__ float update_s;
__shared__ float t_col[W];
__shared__ float t_scratch[W * REDUCE_WARPS];
__shared__ float tau_j_s;
float* a = h + static_cast<long long>(b) * N * N;
float* t = tau + static_cast<long long>(b) * N;
float* tb = t_panel_out + static_cast<long long>(b) * W * W;
const int rows = N - k;
for (int idx = tid; idx < rows * W; idx += blockDim.x) {
const int row = idx / W;
const int col = idx - row * W;
panel[col * N + row] = a[(k + row) * N + (k + col)];
}
__syncthreads();
#pragma unroll
for (int jj = 0; jj < W; ++jj) {
float tail_local = 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
const float x = panel[jj * N + row];
tail_local += x * x;
}
const float tail_norm_sq = block_sum_tid0_f32(tail_local, scratch);
if (tid == 0) {
const float alpha = panel[jj * N + jj];
if (tail_norm_sq == 0.0f) {
beta_s = alpha;
tau_s = 0.0f;
inv_s = 0.0f;
} else {
const float norm = sqrtf(alpha * alpha + tail_norm_sq);
const float beta = (alpha >= 0.0f) ? -norm : norm;
beta_s = beta;
tau_s = (beta - alpha) / beta;
inv_s = 1.0f / (alpha - beta);
}
t[k + jj] = tau_s;
}
__syncthreads();
if (tau_s != 0.0f) {
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[jj * N + row] *= inv_s;
}
}
__syncthreads();
if (tau_s != 0.0f) {
#pragma unroll
for (int j2 = jj + 1; j2 < W; ++j2) {
float dot_local = (tid == 0) ? panel[j2 * N + jj] : 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
dot_local += panel[jj * N + row] * panel[j2 * N + row];
}
const float dot = block_sum_tid0_f32(dot_local, scratch);
if (tid == 0) {
update_s = tau_s * static_cast<float>(dot);
panel[j2 * N + jj] -= update_s;
}
__syncthreads();
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[j2 * N + row] -= panel[jj * N + row] * update_s;
}
}
__syncthreads();
}
if (tid == 0) {
panel[jj * N + jj] = beta_s;
}
__syncthreads();
}
for (int idx = tid; idx < rows * W; idx += blockDim.x) {
const int row = idx / W;
const int col = idx - row * W;
a[(k + row) * N + (k + col)] = panel[col * N + row];
}
for (int idx = tid; idx < W * W; idx += blockDim.x) {
tb[idx] = 0.0f;
}
__syncthreads();
#pragma unroll
for (int j = 0; j < W; ++j) {
if (tid == 0) {
tau_j_s = t[k + j];
}
__syncthreads();
if (j > 0 && tau_j_s != 0.0f) {
#pragma unroll
for (int i = 0; i < j; ++i) {
float local = 0.0f;
for (int row = j + tid; row < rows; row += blockDim.x) {
const float vi = panel[i * N + row];
float vj = 0.0f;
if (row == j) {
vj = 1.0f;
} else if (row > j) {
vj = panel[j * N + row];
}
local += vi * vj;
}
const float dot = block_sum_tid0_f32(local, t_scratch + i * REDUCE_WARPS);
if (tid == 0) {
t_col[i] = -tau_j_s * static_cast<float>(dot);
}
}
__syncthreads();
for (int i = tid; i < j; i += blockDim.x) {
float acc = 0.0f;
#pragma unroll
for (int q = 0; q < j; ++q) {
acc += tb[i * W + q] * t_col[q];
}
tb[i * W + j] = acc;
}
__syncthreads();
}
if (tid == 0) {
tb[j * W + j] = tau_j_s;
}
__syncthreads();
}
}
template <int N, int W>
__global__ void __launch_bounds__(THREADS, 2) geqrf_panel_smem_dynamic_kernel(float* __restrict__ h,
float* __restrict__ tau,
float* __restrict__ v_panel_out,
float* __restrict__ t_panel_out,
int batch,
int k,
int width) {
const int b = blockIdx.x;
const int tid = threadIdx.x;
if (b >= batch) {
return;
}
extern __shared__ float panel[];
__shared__ float scratch[REDUCE_WARPS];
__shared__ float beta_s;
__shared__ float tau_s;
__shared__ float inv_s;
__shared__ float update_s;
__shared__ float t_col[W];
__shared__ float tau_j_s;
float* a = h + static_cast<long long>(b) * N * N;
float* t = tau + static_cast<long long>(b) * N;
const int rows = N - k;
float* vp = v_panel_out == nullptr ? nullptr : v_panel_out + static_cast<long long>(b) * rows * width;
float* tb = t_panel_out == nullptr ? nullptr : t_panel_out + static_cast<long long>(b) * width * width;
for (int idx = tid; idx < rows * width; idx += blockDim.x) {
const int row = idx / width;
const int col = idx - row * width;
panel[col * N + row] = a[(k + row) * N + (k + col)];
}
__syncthreads();
for (int jj = 0; jj < width; ++jj) {
float tail_local = 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
const float x = panel[jj * N + row];
tail_local += x * x;
}
const float tail_norm_sq = block_sum_tid0_f32(tail_local, scratch);
if (tid == 0) {
const float alpha = panel[jj * N + jj];
if (tail_norm_sq == 0.0f) {
beta_s = alpha;
tau_s = 0.0f;
inv_s = 0.0f;
} else {
const float norm = sqrtf(alpha * alpha + tail_norm_sq);
const float beta = (alpha >= 0.0f) ? -norm : norm;
beta_s = beta;
tau_s = (beta - alpha) / beta;
inv_s = 1.0f / (alpha - beta);
}
t[k + jj] = tau_s;
}
__syncthreads();
if (tau_s != 0.0f) {
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[jj * N + row] *= inv_s;
}
}
__syncthreads();
if (tau_s != 0.0f) {
for (int j2 = jj + 1; j2 < width; ++j2) {
float dot_local = (tid == 0) ? panel[j2 * N + jj] : 0.0f;
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
dot_local += panel[jj * N + row] * panel[j2 * N + row];
}
const float dot = block_sum_tid0_f32(dot_local, scratch);
if (tid == 0) {
update_s = tau_s * static_cast<float>(dot);
panel[j2 * N + jj] -= update_s;
}
__syncthreads();
for (int row = jj + 1 + tid; row < rows; row += blockDim.x) {
panel[j2 * N + row] -= panel[jj * N + row] * update_s;
}
}
__syncthreads();
}
if (tid == 0) {
panel[jj * N + jj] = beta_s;
}
__syncthreads();
}
for (int idx = tid; idx < rows * width; idx += blockDim.x) {
const int row = idx / width;
const int col = idx - row * width;
a[(k + row) * N + (k + col)] = panel[col * N + row];
}
if (vp != nullptr) {
for (int idx = tid; idx < rows * width; idx += blockDim.x) {
const int row = idx / width;
const int col = idx - row * width;
float value = 0.0f;
if (row == col) {
value = 1.0f;
} else if (row > col) {
value = panel[col * N + row];
}
vp[row * width + col] = value;
}
}
if (tb != nullptr) {
for (int idx = tid; idx < width * width; idx += blockDim.x) {
tb[idx] = 0.0f;
}
__syncthreads();
for (int j = 0; j < width; ++j) {
if (tid == 0) {
tau_j_s = t[k + j];
}
__syncthreads();
if (j > 0 && tau_j_s != 0.0f) {
for (int i = 0; i < j; ++i) {
float local = 0.0f;
for (int row = j + tid; row < rows; row += blockDim.x) {
float vi = 0.0f;
if (row == i) {
vi = 1.0f;
} else if (row > i) {
vi = panel[i * N + row];
}
float vj = 0.0f;
if (row == j) {
vj = 1.0f;
} else if (row > j) {
vj = panel[j * N + row];
}
local += vi * vj;
}
const float dot = block_sum_f32(local, scratch);
if (tid == 0) {
t_col[i] = -tau_j_s * static_cast<float>(dot);
}
}
__syncthreads();
for (int i = tid; i < j; i += blockDim.x) {
float acc = 0.0f;
for (int q = 0; q < j; ++q) {
acc += tb[i * width + q] * t_col[q];
}
tb[i * width + j] = acc;
}
__syncthreads();
}
if (tid == 0) {
tb[j * width + j] = tau_j_s;
}
__syncthreads();
}
}
}
__global__ void make_t_panel_kernel(const float* __restrict__ v,
const float* __restrict__ tau,
float* __restrict__ t,
int batch,
int rows,
int width,
long long tau_s0,
long long tau_s1) {
const int b = blockIdx.x;
const int tid = threadIdx.x;
if (b >= batch) {
return;
}
__shared__ float scratch[REDUCE_WARPS];
__shared__ float col[MAX_PANEL];
__shared__ float tau_j_s;
const float* vb = v + static_cast<long long>(b) * rows * width;
const float* taub = tau + static_cast<long long>(b) * tau_s0;
float* tb = t + static_cast<long long>(b) * width * width;
for (int idx = tid; idx < width * width; idx += blockDim.x) {
tb[idx] = 0.0f;
}
__syncthreads();
for (int j = 0; j < width; ++j) {
if (tid == 0) {
tau_j_s = taub[static_cast<long long>(j) * tau_s1];
}
__syncthreads();
if (j > 0 && tau_j_s != 0.0f) {
for (int i = 0; i < j; ++i) {
float local = 0.0f;
for (int row = j + tid; row < rows; row += blockDim.x) {
local += vb[row * width + i] * vb[row * width + j];
}
const float dot = block_sum_f32(local, scratch);
if (tid == 0) {
col[i] = -tau_j_s * static_cast<float>(dot);
}
}
__syncthreads();
for (int i = tid; i < j; i += blockDim.x) {
float acc = 0.0f;
for (int q = 0; q < j; ++q) {
acc += tb[i * width + q] * col[q];
}
tb[i * width + j] = acc;
}
__syncthreads();
}
if (tid == 0) {
tb[j * width + j] = tau_j_s;
}
__syncthreads();
}
}
__global__ void pack_v_panel_kernel(const float* __restrict__ h,
float* __restrict__ v,
int batch,
int n,
int rows,
int k,
int width) {
const int b = blockIdx.z;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
const int col = blockIdx.x * blockDim.x + threadIdx.x;
if (b >= batch || row >= rows || col >= width) {
return;
}
float value = 0.0f;
if (row == col) {
value = 1.0f;
} else if (row > col) {
value = h[(static_cast<long long>(b) * n + (k + row)) * n + (k + col)];
}
v[(static_cast<long long>(b) * rows + row) * width + col] = value;
}
__global__ void pack_v_panel_half_kernel(const float* __restrict__ h,
float* __restrict__ v,
__half* __restrict__ vh,
int batch,
int n,
int rows,
int k,
int width) {
const int b = blockIdx.z;
const int row = blockIdx.y * blockDim.y + threadIdx.y;
const int col = blockIdx.x * blockDim.x + threadIdx.x;
if (b >= batch || row >= rows || col >= width) {
return;
}
float value = 0.0f;
if (row == col) {
value = 1.0f;
} else if (row > col) {
value = h[(static_cast<long long>(b) * n + (k + row)) * n + (k + col)];
}
const long long idx = (static_cast<long long>(b) * rows + row) * width + col;
v[idx] = value;
vh[idx] = __float2half(value);
}
__global__ void update_512_w16_hacc_kernel(float* __restrict__ h,
const __half* __restrict__ v,
const __half* __restrict__ work,
int batch,
int k,
int next_col) {
constexpr int N = 512;
constexpr int W = 16;
constexpr int TILE = 16;
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int row = blockIdx.y * TILE + ty;
const int col = blockIdx.x * TILE + tx;
const int b = blockIdx.z;
const int rows = N - k;
const int cols = N - next_col;
if (b >= batch || row >= rows || col >= cols) {
return;
}
const __half* vb = v + static_cast<long long>(b) * rows * W;
const __half* wb = work + static_cast<long long>(b) * W * cols;
float acc = 0.0f;
#pragma unroll
for (int j = 0; j < W; ++j) {
acc += __half2float(vb[row * W + j]) * __half2float(wb[j * cols + col]);
}
float* a = h + static_cast<long long>(b) * N * N;
a[(k + row) * N + (next_col + col)] -= acc;
}
template <int N>
__global__ void update_w16_hmma_kernel(float* __restrict__ h,
const __half* __restrict__ v,
const __half* __restrict__ work,
int batch,
int k,
int next_col) {
constexpr int W = 16;
constexpr int TILE = 16;
constexpr int WARPS = 8;
const int warp = threadIdx.x >> 5;
const int lane = threadIdx.x & 31;
const int tile_col = blockIdx.x * WARPS + warp;
const int tile_row = blockIdx.y;
const int b = blockIdx.z;
if (b >= batch) {
return;
}
const int rows = N - k;
const int cols = N - next_col;
const int row0 = tile_row * TILE;
const int col0 = tile_col * TILE;
if (row0 >= rows || col0 >= cols) {
return;
}
const __half* vb = v + static_cast<long long>(b) * rows * W + row0 * W;
const __half* wb = work + static_cast<long long>(b) * W * cols + col0;
wmma::fragment<wmma::matrix_a, TILE, TILE, TILE, __half, wmma::row_major> a_frag;
wmma::fragment<wmma::matrix_b, TILE, TILE, TILE, __half, wmma::row_major> b_frag;
wmma::fragment<wmma::accumulator, TILE, TILE, TILE, float> c_frag;
wmma::fill_fragment(c_frag, 0.0f);
wmma::load_matrix_sync(a_frag, vb, W);
wmma::load_matrix_sync(b_frag, wb, cols);
wmma::mma_sync(c_frag, a_frag, b_frag, c_frag);
__shared__ float tile[WARPS * TILE * TILE];
float* tile_w = tile + warp * TILE * TILE;
wmma::store_matrix_sync(tile_w, c_frag, TILE, wmma::mem_row_major);
__syncthreads();
float* out = h + static_cast<long long>(b) * N * N + static_cast<long long>(k + row0) * N + (next_col + col0);
for (int idx = lane; idx < TILE * TILE; idx += 32) {
const int r = idx / TILE;
const int c = idx - r * TILE;
out[r * N + c] -= tile_w[idx];
}
}
__global__ void update_512_w16_active_wmma_kernel(float* __restrict__ h,
const __half* __restrict__ v,
const __half* __restrict__ work,
const int* __restrict__ active_cols,
int batch,
int k,
int next_col) {
constexpr int N = 512;
constexpr int W = 16;
constexpr int TILE = 16;
constexpr int WARPS = 8;
const int warp = threadIdx.x >> 5;
const int lane = threadIdx.x & 31;
const int tile_col = blockIdx.x * WARPS + warp;
const int tile_row = blockIdx.y;
const int b = blockIdx.z;
if (b >= batch || warp >= WARPS) {
return;
}
const int rows = N - k;
const int cols = N - next_col;
const int row0 = tile_row * TILE;
const int col0 = tile_col * TILE;
const int active = active_cols[b];
const bool valid_tile = row0 < rows && col0 < cols && next_col + col0 < active;
const __half* vb = v + static_cast<long long>(b) * rows * W + row0 * W;
const __half* wb = work + static_cast<long long>(b) * W * cols + col0;
__shared__ float tile[WARPS * TILE * TILE];
float* tile_w = tile + warp * TILE * TILE;
for (int idx = lane; idx < TILE * TILE; idx += 32) {
tile_w[idx] = 0.0f;
}
if (valid_tile) {
wmma::fragment<wmma::matrix_a, TILE, TILE, TILE, __half, wmma::row_major> a_frag;
wmma::fragment<wmma::matrix_b, TILE, TILE, TILE, __half, wmma::row_major> b_frag;
wmma::fragment<wmma::accumulator, TILE, TILE, TILE, float> c_frag;
wmma::fill_fragment(c_frag, 0.0f);
wmma::load_matrix_sync(a_frag, vb, W);
wmma::load_matrix_sync(b_frag, wb, cols);
wmma::mma_sync(c_frag, a_frag, b_frag, c_frag);
wmma::store_matrix_sync(tile_w, c_frag, TILE, wmma::mem_row_major);
}
__syncthreads();
float* out = h + static_cast<long long>(b) * N * N + static_cast<long long>(k + row0) * N + (next_col + col0);
for (int idx = lane; idx < TILE * TILE; idx += 32) {
const int r = idx / TILE;
const int c = idx - r * TILE;
if (valid_tile && row0 + r < rows && col0 + c < cols && next_col + col0 + c < active) {
out[r * N + c] -= tile_w[idx];
}
}
}
__global__ void setup_512_w16_active_grouped_kernel(const __half* __restrict__ v,
const __half* __restrict__ work,
float* __restrict__ h,
const int* __restrict__ active_cols,
cutlass::gemm::GemmCoord* __restrict__ problem_sizes,
Cutlass512ElementA** __restrict__ ptr_a,
Cutlass512ElementB** __restrict__ ptr_b,
Cutlass512ElementC** __restrict__ ptr_c,
Cutlass512ElementC** __restrict__ ptr_d,
int64_t* __restrict__ lda,
int64_t* __restrict__ ldb,
int64_t* __restrict__ ldc,
int64_t* __restrict__ ldd,
int batch,
int k,
int next_col,
int cols,
int v_col_stride,
int work_row_stride) {
constexpr int N = 512;
constexpr int W = 16;
const int b = blockIdx.x * blockDim.x + threadIdx.x;
if (b >= batch) {
return;
}
const int rows = N - k;
int active = active_cols[b] - next_col;
if (active < 0) {
active = 0;
}
if (active > cols) {
active = cols;
}
problem_sizes[b] = cutlass::gemm::GemmCoord(rows, active, W);
ptr_a[b] = reinterpret_cast<Cutlass512ElementA*>(const_cast<__half*>(v + static_cast<long long>(b) * rows * v_col_stride));
ptr_b[b] = reinterpret_cast<Cutlass512ElementB*>(const_cast<__half*>(work + static_cast<long long>(b) * work_row_stride * cols));
Cutlass512ElementC* c_ptr = h + static_cast<long long>(b) * N * N + static_cast<long long>(k) * N + next_col;
ptr_c[b] = c_ptr;
ptr_d[b] = c_ptr;
lda[b] = v_col_stride;
ldb[b] = cols;
ldc[b] = N;
ldd[b] = N;
}
__global__ void update_512_w16_fused_kernel(float* __restrict__ h,
const float* __restrict__ v,
const float* __restrict__ t,
int batch,
int k,
int next_col) {
constexpr int N = 512;
constexpr int W = 16;
constexpr int TILE_COLS = 16;
const int tid = threadIdx.x;
const int b = blockIdx.y;
const int col0 = blockIdx.x * TILE_COLS;
if (b >= batch) {
return;
}
const int rows = N - k;
const int cols = N - next_col;
if (col0 >= cols) {
return;
}
const float* vb = v + static_cast<long long>(b) * rows * W;
const float* tb = t + static_cast<long long>(b) * W * W;
float* a = h + static_cast<long long>(b) * N * N;
__shared__ float dots[W * TILE_COLS];
__shared__ float work[W * TILE_COLS];
if (tid < W * TILE_COLS) {
const int j = tid / TILE_COLS;
const int c = tid - j * TILE_COLS;
const int col = col0 + c;
float acc = 0.0f;
if (col < cols) {
#pragma unroll 1
for (int row = 0; row < rows; ++row) {
acc += vb[row * W + j] * a[(k + row) * N + (next_col + col)];
}
}
dots[j * TILE_COLS + c] = acc;
}
__syncthreads();
if (tid < W * TILE_COLS) {
const int q = tid / TILE_COLS;
const int c = tid - q * TILE_COLS;
float acc = 0.0f;
#pragma unroll
for (int j = 0; j < W; ++j) {
acc += tb[j * W + q] * dots[j * TILE_COLS + c];
}
work[q * TILE_COLS + c] = acc;
}
__syncthreads();
for (int idx = tid; idx < rows * TILE_COLS; idx += blockDim.x) {
const int row = idx / TILE_COLS;
const int c = idx - row * TILE_COLS;
const int col = col0 + c;
if (col < cols) {
float acc = 0.0f;
#pragma unroll
for (int q = 0; q < W; ++q) {
acc += vb[row * W + q] * work[q * TILE_COLS + c];
}
a[(k + row) * N + (next_col + col)] -= acc;
}
}
}
__global__ void update_512_w32_active_kernel(float* __restrict__ h,
const float* __restrict__ v,
const float* __restrict__ t,
const int* __restrict__ active_cols,
int batch,
int k,
int next_col) {
constexpr int N = 512;
constexpr int W = 32;
constexpr int TILE_COLS = 8;
const int tid = threadIdx.x;
const int warp = tid >> 5;
const int lane = tid & 31;
const int b = blockIdx.y;
const int local_col = blockIdx.x * TILE_COLS + warp;
const int actual_col = next_col + local_col;
if (b >= batch || warp >= TILE_COLS) {
return;
}
const int rows = N - k;
const int cols = N - next_col;
const int active = active_cols[b];
const bool valid_col = local_col < cols && actual_col < active;
const float* vb = v + static_cast<long long>(b) * rows * W;
const float* tb = t + static_cast<long long>(b) * W * W;
float* a = h + static_cast<long long>(b) * N * N;
__shared__ float v_tile[32][W];
__shared__ float t_t[W][W];
__shared__ float dots[TILE_COLS][W];
__shared__ float work[TILE_COLS][W];
for (int idx = tid; idx < W * W; idx += blockDim.x) {
const int row = idx / W;
const int col = idx - row * W;
t_t[col][row] = tb[row * W + col];
}
__syncthreads();
float dot_acc[W];
#pragma unroll
for (int j = 0; j < W; ++j) {
dot_acc[j] = 0.0f;
}
for (int row_base = 0; row_base < rows; row_base += 32) {
for (int idx = tid; idx < 32 * W; idx += blockDim.x) {
const int rr = idx / W;
const int q = idx - rr * W;
const int row = row_base + rr;
v_tile[rr][q] = row < rows ? vb[row * W + q] : 0.0f;
}
__syncthreads();
if (valid_col) {
const int row = row_base + lane;
const float aval = row < rows ? a[(k + row) * N + actual_col] : 0.0f;
#pragma unroll
for (int j = 0; j < W; ++j) {
dot_acc[j] += v_tile[lane][j] * aval;
}
}
__syncthreads();
}
#pragma unroll
for (int j = 0; j < W; ++j) {
const float acc = warp_sum_f32(dot_acc[j]);
if (lane == 0) {
dots[warp][j] = acc;
}
}
__syncthreads();
if (lane < W) {
float acc = 0.0f;
#pragma unroll
for (int j = 0; j < W; ++j) {
acc += t_t[lane][j] * dots[warp][j];
}
work[warp][lane] = acc;
}
__syncthreads();
for (int row_base = 0; row_base < rows; row_base += 32) {
for (int idx = tid; idx < 32 * W; idx += blockDim.x) {
const int rr = idx / W;
const int q = idx - rr * W;
const int row = row_base + rr;
v_tile[rr][q] = row < rows ? vb[row * W + q] : 0.0f;
}
__syncthreads();
if (valid_col) {
const int row = row_base + lane;
if (row < rows) {
float acc = 0.0f;
#pragma unroll
for (int q = 0; q < W; ++q) {
acc += v_tile[lane][q] * work[warp][q];
}
a[(k + row) * N + actual_col] -= acc;
}
}
__syncthreads();
}
}
__global__ void update_2048_w4_kernel(float* __restrict__ h,
const float* __restrict__ v,
const float* __restrict__ t,
int batch,
int k,
int next_col) {
constexpr int N = 2048;
constexpr int W = 4;
const int col = next_col + blockIdx.x;
const int b = blockIdx.y;
const int tid = threadIdx.x;
if (b >= batch || col >= N) {
return;
}
__shared__ float scratch[REDUCE_WARPS];
__shared__ float dots[W];
__shared__ float y[W];
const int rows = N - k;
const float* vb = v + static_cast<long long>(b) * rows * W;
const float* tb = t + static_cast<long long>(b) * W * W;
float* a = h + static_cast<long long>(b) * N * N;
for (int j = 0; j < W; ++j) {
float local = 0.0f;
for (int row = tid; row < rows; row += blockDim.x) {
local += vb[row * W + j] * a[(k + row) * N + col];
}
const float dot = block_sum_tid0_f32(local, scratch);
if (tid == 0) {
dots[j] = dot;
}
__syncthreads();
}
if (tid < W) {
float acc = 0.0f;
for (int q = 0; q < W; ++q) {
acc += tb[q * W + tid] * dots[q];
}
y[tid] = acc;
}
__syncthreads();
for (int row = tid; row < rows; row += blockDim.x) {
float acc = 0.0f;
for (int j = 0; j < W; ++j) {
acc += vb[row * W + j] * y[j];
}
a[(k + row) * N + col] -= acc;
}
}
template <int W>
__global__ void update_2048_w_tile8_kernel(float* __restrict__ h,
const float* __restrict__ v,
const float* __restrict__ t,
int batch,
int k,
int next_col) {
constexpr int N = 2048;
constexpr int TILE_COLS = 8;
const int tid = threadIdx.x;
const int lane = tid & 31;
const int warp = tid >> 5;
const int col = next_col + blockIdx.x * TILE_COLS + warp;
const int b = blockIdx.y;
if (b >= batch || warp >= TILE_COLS) {
return;
}
__shared__ float dots[W][TILE_COLS];
__shared__ float y[W][TILE_COLS];
const int rows = N - k;
const bool valid_col = col < N;
const float* vb = v + static_cast<long long>(b) * rows * W;
const float* tb = t + static_cast<long long>(b) * W * W;
float* a = h + static_cast<long long>(b) * N * N;
for (int j = 0; j < W; ++j) {
float local = 0.0f;
if (valid_col) {
for (int row = lane; row < rows; row += 32) {
local += vb[row * W + j] * a[(k + row) * N + col];
}
}
local = warp_sum_f32(local);
if (lane == 0) {
dots[j][warp] = local;
}
__syncthreads();
}
if (lane == 0) {
for (int j = 0; j < W; ++j) {
float acc = 0.0f;
for (int q = 0; q < W; ++q) {
acc += tb[q * W + j] * dots[q][warp];
}
y[j][warp] = acc;
}
}
__syncthreads();
if (valid_col) {
for (int row = lane; row < rows; row += 32) {
float acc = 0.0f;
for (int j = 0; j < W; ++j) {
acc += vb[row * W + j] * y[j][warp];
}
a[(k + row) * N + col] -= acc;
}
}
}
} // namespace
template <int N>
void geqrf_panel(torch::Tensor h, torch::Tensor tau, torch::Tensor t_panel, int64_t k, int64_t width, const char* name) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), name, " expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == N && h.size(2) == N, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == N, "tau has wrong shape");
float* t_ptr = nullptr;
if (t_panel.defined()) {
TORCH_CHECK(t_panel.is_cuda(), name, " t expects CUDA tensor");
TORCH_CHECK(t_panel.scalar_type() == torch::kFloat32, "t must be float32");
TORCH_CHECK(t_panel.is_contiguous(), "t must be contiguous");
TORCH_CHECK(t_panel.dim() == 3, "t must be batch x width x width");
t_ptr = t_panel.data_ptr<float>();
}
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww > 0 && ww <= MAX_PANEL, "invalid panel width");
TORCH_CHECK(kk >= 0 && kk + ww <= N, "invalid panel offset");
const int batch = static_cast<int>(h.size(0));
if (t_panel.defined()) {
TORCH_CHECK(t_panel.size(0) == batch && t_panel.size(1) == ww && t_panel.size(2) == ww, "t has wrong shape");
}
if (batch == 0) {
return;
}
if (t_panel.defined()) {
geqrf_panel_kernel<N, true><<<batch, THREADS>>>(h.data_ptr<float>(), tau.data_ptr<float>(), t_ptr, batch, kk, ww);
} else {
geqrf_panel_kernel<N, false><<<batch, THREADS>>>(h.data_ptr<float>(), tau.data_ptr<float>(), nullptr, batch, kk, ww);
}
check_cuda(cudaGetLastError(), name);
}
void geqrf_32_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
geqrf_panel<32>(h, tau, torch::Tensor(), k, width, "geqrf_32_panel");
}
void geqrf_32_warp(torch::Tensor h, torch::Tensor tau) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "geqrf_32_warp expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 32 && h.size(2) == 32, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(0) == h.size(0) && tau.size(1) == 32, "tau has wrong shape");
const int batch = static_cast<int>(h.size(0));
if (batch == 0) {
return;
}
constexpr int WARPS_PER_BLOCK = 8;
constexpr int THREADS_PER_BLOCK = 32 * WARPS_PER_BLOCK;
const int blocks = (batch + WARPS_PER_BLOCK - 1) / WARPS_PER_BLOCK;
geqrf_32_warp_kernel<<<blocks, THREADS_PER_BLOCK>>>(nullptr, h.data_ptr<float>(), tau.data_ptr<float>(), batch);
check_cuda(cudaGetLastError(), "geqrf_32_warp");
}
void geqrf_32_warp_out(torch::Tensor input, torch::Tensor h, torch::Tensor tau) {
TORCH_CHECK(input.is_cuda() && h.is_cuda() && tau.is_cuda(), "geqrf_32_warp_out expects CUDA tensors");
TORCH_CHECK(input.scalar_type() == torch::kFloat32, "input must be float32");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(input.is_contiguous(), "input must be contiguous");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(input.dim() == 3 && input.size(1) == 32 && input.size(2) == 32, "input has wrong shape");
TORCH_CHECK(h.dim() == 3 && h.size(0) == input.size(0) && h.size(1) == 32 && h.size(2) == 32, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(0) == input.size(0) && tau.size(1) == 32, "tau has wrong shape");
const int batch = static_cast<int>(input.size(0));
if (batch == 0) {
return;
}
constexpr int WARPS_PER_BLOCK = 8;
constexpr int THREADS_PER_BLOCK = 32 * WARPS_PER_BLOCK;
const int blocks = (batch + WARPS_PER_BLOCK - 1) / WARPS_PER_BLOCK;
geqrf_32_warp_kernel<<<blocks, THREADS_PER_BLOCK>>>(
input.data_ptr<float>(),
h.data_ptr<float>(),
tau.data_ptr<float>(),
batch);
check_cuda(cudaGetLastError(), "geqrf_32_warp_out");
}
std::tuple<torch::Tensor, torch::Tensor> geqrf_32_warp_make(torch::Tensor input) {
TORCH_CHECK(input.is_cuda(), "geqrf_32_warp_make expects CUDA input");
TORCH_CHECK(input.scalar_type() == torch::kFloat32, "input must be float32");
TORCH_CHECK(input.is_contiguous(), "input must be contiguous");
TORCH_CHECK(input.dim() == 3 && input.size(1) == 32 && input.size(2) == 32, "input has wrong shape");
auto h = torch::empty_like(input);
auto tau = torch::empty({input.size(0), 32}, input.options());
const int batch = static_cast<int>(input.size(0));
if (batch > 0) {
constexpr int WARPS_PER_BLOCK = 8;
constexpr int THREADS_PER_BLOCK = 32 * WARPS_PER_BLOCK;
const int blocks = (batch + WARPS_PER_BLOCK - 1) / WARPS_PER_BLOCK;
geqrf_32_warp_kernel<<<blocks, THREADS_PER_BLOCK>>>(
input.data_ptr<float>(),
h.data_ptr<float>(),
tau.data_ptr<float>(),
batch);
check_cuda(cudaGetLastError(), "geqrf_32_warp_make");
}
return std::make_tuple(h, tau);
}
void geqrf_176_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
geqrf_panel<176>(h, tau, torch::Tensor(), k, width, "geqrf_176_panel");
}
void geqrf_176_panel_smem_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t_panel, int64_t k, int64_t width) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda() && t_panel.is_cuda(), "geqrf_176_panel_smem_t expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(t_panel.scalar_type() == torch::kFloat32, "t_panel must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(t_panel.is_contiguous(), "t_panel must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 176 && h.size(2) == 176, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 176, "tau has wrong shape");
TORCH_CHECK(t_panel.dim() == 3 && t_panel.size(1) == 8 && t_panel.size(2) == 8, "t_panel has wrong shape");
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww == 8, "geqrf_176_panel_smem_t requires width 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 176, "invalid panel offset");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(t_panel.size(0) == batch, "t_panel batch mismatch");
if (batch == 0) {
return;
}
geqrf_176_panel_smem_t_kernel<<<batch, THREADS_176_PANEL>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
nullptr,
t_panel.data_ptr<float>(),
batch,
kk);
check_cuda(cudaGetLastError(), "geqrf_176_panel_smem_t");
}
void geqrf_176_panel_smem_pack_t(torch::Tensor h, torch::Tensor tau, torch::Tensor v_panel, torch::Tensor t_panel, int64_t k, int64_t width) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda() && v_panel.is_cuda() && t_panel.is_cuda(), "geqrf_176_panel_smem_pack_t expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(v_panel.scalar_type() == torch::kFloat32, "v_panel must be float32");
TORCH_CHECK(t_panel.scalar_type() == torch::kFloat32, "t_panel must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(v_panel.is_contiguous(), "v_panel must be contiguous");
TORCH_CHECK(t_panel.is_contiguous(), "t_panel must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 176 && h.size(2) == 176, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 176, "tau has wrong shape");
TORCH_CHECK(v_panel.dim() == 3 && v_panel.size(2) == 8, "v_panel has wrong shape");
TORCH_CHECK(t_panel.dim() == 3 && t_panel.size(1) == 8 && t_panel.size(2) == 8, "t_panel has wrong shape");
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww == 8, "geqrf_176_panel_smem_pack_t requires width 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 176, "invalid panel offset");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(v_panel.size(0) == batch && v_panel.size(1) == 176 - kk, "v_panel batch/rows mismatch");
TORCH_CHECK(t_panel.size(0) == batch, "t_panel batch mismatch");
if (batch == 0) {
return;
}
geqrf_176_panel_smem_t_kernel<<<batch, THREADS_176_PANEL>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
v_panel.data_ptr<float>(),
t_panel.data_ptr<float>(),
batch,
kk);
check_cuda(cudaGetLastError(), "geqrf_176_panel_smem_pack_t");
}
void geqrf_352_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
geqrf_panel<352>(h, tau, torch::Tensor(), k, width, "geqrf_352_panel");
}
void geqrf_352_panel_smem_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t_panel, int64_t k, int64_t width) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda() && t_panel.is_cuda(), "geqrf_352_panel_smem_t expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(t_panel.scalar_type() == torch::kFloat32, "t_panel must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(t_panel.is_contiguous(), "t_panel must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 352 && h.size(2) == 352, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 352, "tau has wrong shape");
TORCH_CHECK(t_panel.dim() == 3 && t_panel.size(1) == 8 && t_panel.size(2) == 8, "t_panel has wrong shape");
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww == 8, "geqrf_352_panel_smem_t requires width 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 352, "invalid panel offset");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(t_panel.size(0) == batch, "t_panel batch mismatch");
if (batch == 0) {
return;
}
geqrf_352_panel_smem_t_kernel<<<batch, THREADS>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
t_panel.data_ptr<float>(),
batch,
kk);
check_cuda(cudaGetLastError(), "geqrf_352_panel_smem_t");
}
void geqrf_512_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
geqrf_panel<512>(h, tau, torch::Tensor(), k, width, "geqrf_512_panel");
}
void geqrf_512_panel_smem(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "geqrf_512_panel_smem expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 512 && h.size(2) == 512, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 512, "tau has wrong shape");
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww == 8, "geqrf_512_panel_smem requires width 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 512, "invalid panel offset");
const int batch = static_cast<int>(h.size(0));
if (batch == 0) {
return;
}
geqrf_512_panel_smem_kernel<<<batch, THREADS>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
nullptr,
nullptr,
nullptr,
nullptr,
batch,
kk,
ww,
kk,
ww,
0);
check_cuda(cudaGetLastError(), "geqrf_512_panel_smem");
}
void geqrf_512_panel_smem_pack(torch::Tensor h,
torch::Tensor tau,
int64_t k,
int64_t width,
torch::Tensor v_panel,
torch::Tensor v_block,
torch::Tensor t_panel,
int64_t block_k,
int64_t out_col) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda() && v_panel.is_cuda() && v_block.is_cuda() && t_panel.is_cuda(), "geqrf_512_panel_smem_pack expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(v_panel.scalar_type() == torch::kFloat32, "v_panel must be float32");
TORCH_CHECK(v_block.scalar_type() == torch::kFloat32, "v_block must be float32");
TORCH_CHECK(t_panel.scalar_type() == torch::kFloat32, "t_panel must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(v_panel.is_contiguous(), "v_panel must be contiguous");
TORCH_CHECK(v_block.is_contiguous(), "v_block must be contiguous");
TORCH_CHECK(t_panel.is_contiguous(), "t_panel must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 512 && h.size(2) == 512, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 512, "tau has wrong shape");
TORCH_CHECK(v_panel.dim() == 3 && v_block.dim() == 3, "v outputs must be batch x rows x width");
TORCH_CHECK(t_panel.dim() == 3, "t_panel must be batch x width x width");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
const int bk = static_cast<int>(block_k);
const int oc = static_cast<int>(out_col);
TORCH_CHECK(ww == 8, "geqrf_512_panel_smem_pack requires width 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 512, "invalid panel offset");
TORCH_CHECK(bk >= 0 && bk <= kk, "invalid block offset");
TORCH_CHECK(oc == kk - bk, "out_col must match k - block_k");
TORCH_CHECK(v_panel.size(0) == batch && v_panel.size(1) == 512 - kk && v_panel.size(2) == ww, "v_panel has wrong shape");
TORCH_CHECK(v_block.size(0) == batch && v_block.size(1) == 512 - bk && v_block.size(2) >= oc + ww, "v_block has wrong shape");
TORCH_CHECK(t_panel.size(0) == batch && t_panel.size(1) == ww && t_panel.size(2) == ww, "t_panel has wrong shape");
if (batch == 0) {
return;
}
geqrf_512_panel_smem_kernel<<<batch, THREADS>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
v_panel.data_ptr<float>(),
v_block.data_ptr<float>(),
nullptr,
t_panel.data_ptr<float>(),
batch,
kk,
ww,
bk,
static_cast<int>(v_block.size(2)),
oc);
check_cuda(cudaGetLastError(), "geqrf_512_panel_smem_pack");
}
void geqrf_512_panel_smem_pack_h(torch::Tensor h,
torch::Tensor tau,
int64_t k,
int64_t width,
torch::Tensor v_panel,
torch::Tensor v_block,
torch::Tensor v_block_h,
torch::Tensor t_panel,
int64_t block_k,
int64_t out_col) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda() && v_panel.is_cuda() && v_block.is_cuda() && v_block_h.is_cuda() && t_panel.is_cuda(), "geqrf_512_panel_smem_pack_h expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(v_panel.scalar_type() == torch::kFloat32, "v_panel must be float32");
TORCH_CHECK(v_block.scalar_type() == torch::kFloat32, "v_block must be float32");
TORCH_CHECK(v_block_h.scalar_type() == torch::kFloat16, "v_block_h must be float16");
TORCH_CHECK(t_panel.scalar_type() == torch::kFloat32, "t_panel must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(v_panel.is_contiguous(), "v_panel must be contiguous");
TORCH_CHECK(v_block.is_contiguous(), "v_block must be contiguous");
TORCH_CHECK(v_block_h.is_contiguous(), "v_block_h must be contiguous");
TORCH_CHECK(t_panel.is_contiguous(), "t_panel must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 512 && h.size(2) == 512, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 512, "tau has wrong shape");
TORCH_CHECK(v_panel.dim() == 3 && v_block.dim() == 3 && v_block_h.dim() == 3, "v outputs must be batch x rows x width");
TORCH_CHECK(t_panel.dim() == 3, "t_panel must be batch x width x width");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
const int bk = static_cast<int>(block_k);
const int oc = static_cast<int>(out_col);
TORCH_CHECK(ww == 8, "geqrf_512_panel_smem_pack_h requires width 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 512, "invalid panel offset");
TORCH_CHECK(bk >= 0 && bk <= kk, "invalid block offset");
TORCH_CHECK(oc == kk - bk, "out_col must match k - block_k");
TORCH_CHECK(v_panel.size(0) == batch && v_panel.size(1) == 512 - kk && v_panel.size(2) == ww, "v_panel has wrong shape");
TORCH_CHECK(v_block.size(0) == batch && v_block.size(1) == 512 - bk && v_block.size(2) >= oc + ww, "v_block has wrong shape");
TORCH_CHECK(v_block_h.size(0) == batch && v_block_h.size(1) == 512 - bk && v_block_h.size(2) >= oc + ww, "v_block_h has wrong shape");
TORCH_CHECK(t_panel.size(0) == batch && t_panel.size(1) == ww && t_panel.size(2) == ww, "t_panel has wrong shape");
if (batch == 0) {
return;
}
geqrf_512_panel_smem_kernel<<<batch, THREADS>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
v_panel.data_ptr<float>(),
v_block.data_ptr<float>(),
reinterpret_cast<__half*>(v_block_h.data_ptr<at::Half>()),
t_panel.data_ptr<float>(),
batch,
kk,
ww,
bk,
static_cast<int>(v_block.size(2)),
oc);
check_cuda(cudaGetLastError(), "geqrf_512_panel_smem_pack_h");
}
void geqrf_1024_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
geqrf_panel<1024>(h, tau, torch::Tensor(), k, width, "geqrf_1024_panel");
}
void geqrf_1024_panel_smem(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "geqrf_1024_panel_smem expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 1024 && h.size(2) == 1024, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 1024, "tau has wrong shape");
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww == 8, "geqrf_1024_panel_smem requires width 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 1024, "invalid panel offset");
const int batch = static_cast<int>(h.size(0));
if (batch == 0) {
return;
}
geqrf_panel_smem_basic_kernel<1024, 8><<<batch, THREADS>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
nullptr,
nullptr,
batch,
kk,
ww);
check_cuda(cudaGetLastError(), "geqrf_1024_panel_smem");
}
void geqrf_2048_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
geqrf_panel<2048>(h, tau, torch::Tensor(), k, width, "geqrf_2048_panel");
}
void geqrf_2048_panel_smem(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "geqrf_2048_panel_smem expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 2048 && h.size(2) == 2048, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 2048, "tau has wrong shape");
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww == 4 || ww == 8, "geqrf_2048_panel_smem requires width 4 or 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 2048, "invalid panel offset");
const int batch = static_cast<int>(h.size(0));
if (batch == 0) {
return;
}
if (ww == 8) {
constexpr int dyn_bytes = 2048 * 8 * static_cast<int>(sizeof(float));
auto kernel = geqrf_panel_smem_dynamic_kernel<2048, 8>;
check_cuda(cudaFuncSetAttribute(
kernel,
cudaFuncAttributeMaxDynamicSharedMemorySize,
dyn_bytes),
"geqrf_2048_panel_smem set dynamic smem");
kernel<<<batch, THREADS, dyn_bytes>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
nullptr,
nullptr,
batch,
kk,
ww);
} else {
geqrf_panel_smem_basic_kernel<2048, 4><<<batch, THREADS>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
nullptr,
nullptr,
batch,
kk,
ww);
}
check_cuda(cudaGetLastError(), "geqrf_2048_panel_smem");
}
void geqrf_2048_panel_smem_pack(torch::Tensor h,
torch::Tensor tau,
int64_t k,
int64_t width,
torch::Tensor v_panel,
torch::Tensor t_panel) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda() && v_panel.is_cuda() && t_panel.is_cuda(), "geqrf_2048_panel_smem_pack expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(v_panel.scalar_type() == torch::kFloat32, "v_panel must be float32");
TORCH_CHECK(t_panel.scalar_type() == torch::kFloat32, "t_panel must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(v_panel.is_contiguous(), "v_panel must be contiguous");
TORCH_CHECK(t_panel.is_contiguous(), "t_panel must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 2048 && h.size(2) == 2048, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 2048, "tau has wrong shape");
TORCH_CHECK(v_panel.dim() == 3 && t_panel.dim() == 3, "outputs have wrong rank");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww == 4 || ww == 8, "geqrf_2048_panel_smem_pack requires width 4 or 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 2048, "invalid panel offset");
TORCH_CHECK(v_panel.size(0) == batch && v_panel.size(1) == 2048 - kk && v_panel.size(2) == ww, "v_panel has wrong shape");
TORCH_CHECK(t_panel.size(0) == batch && t_panel.size(1) == ww && t_panel.size(2) == ww, "t_panel has wrong shape");
if (batch == 0) {
return;
}
if (ww == 8) {
constexpr int dyn_bytes = 2048 * 8 * static_cast<int>(sizeof(float));
auto kernel = geqrf_panel_smem_dynamic_kernel<2048, 8>;
check_cuda(cudaFuncSetAttribute(
kernel,
cudaFuncAttributeMaxDynamicSharedMemorySize,
dyn_bytes),
"geqrf_2048_panel_smem_pack set dynamic smem");
kernel<<<batch, THREADS, dyn_bytes>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
v_panel.data_ptr<float>(),
t_panel.data_ptr<float>(),
batch,
kk,
ww);
} else {
geqrf_panel_smem_basic_kernel<2048, 4><<<batch, THREADS>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
v_panel.data_ptr<float>(),
t_panel.data_ptr<float>(),
batch,
kk,
ww);
}
check_cuda(cudaGetLastError(), "geqrf_2048_panel_smem_pack");
}
void geqrf_4096_panel(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
geqrf_panel<4096>(h, tau, torch::Tensor(), k, width, "geqrf_4096_panel");
}
void geqrf_4096_panel_smem(torch::Tensor h, torch::Tensor tau, int64_t k, int64_t width) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "geqrf_4096_panel_smem expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 4096 && h.size(2) == 4096, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 4096, "tau has wrong shape");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww == 8, "geqrf_4096_panel_smem requires width 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 4096, "invalid panel offset");
if (batch == 0) {
return;
}
constexpr int dyn_bytes = 4096 * 8 * static_cast<int>(sizeof(float));
auto kernel = geqrf_panel_smem_dynamic_kernel<4096, 8>;
check_cuda(cudaFuncSetAttribute(
kernel,
cudaFuncAttributeMaxDynamicSharedMemorySize,
dyn_bytes),
"geqrf_4096_panel_smem set dynamic smem");
kernel<<<batch, THREADS, dyn_bytes>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
nullptr,
nullptr,
batch,
kk,
ww);
check_cuda(cudaGetLastError(), "geqrf_4096_panel_smem");
}
void geqrf_4096_panel_smem_pack(torch::Tensor h,
torch::Tensor tau,
int64_t k,
int64_t width,
torch::Tensor v_panel,
torch::Tensor t_panel) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda() && v_panel.is_cuda() && t_panel.is_cuda(), "geqrf_4096_panel_smem_pack expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(v_panel.scalar_type() == torch::kFloat32, "v_panel must be float32");
TORCH_CHECK(t_panel.scalar_type() == torch::kFloat32, "t_panel must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(v_panel.is_contiguous(), "v_panel must be contiguous");
TORCH_CHECK(t_panel.is_contiguous(), "t_panel must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 4096 && h.size(2) == 4096, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 4096, "tau has wrong shape");
TORCH_CHECK(v_panel.dim() == 3 && t_panel.dim() == 3, "outputs have wrong rank");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(ww == 8, "geqrf_4096_panel_smem_pack requires width 8");
TORCH_CHECK(kk >= 0 && kk + ww <= 4096, "invalid panel offset");
TORCH_CHECK(v_panel.size(0) == batch && v_panel.size(1) == 4096 - kk && v_panel.size(2) == ww, "v_panel has wrong shape");
TORCH_CHECK(t_panel.size(0) == batch && t_panel.size(1) == ww && t_panel.size(2) == ww, "t_panel has wrong shape");
if (batch == 0) {
return;
}
constexpr int dyn_bytes = 4096 * 8 * static_cast<int>(sizeof(float));
auto kernel = geqrf_panel_smem_dynamic_kernel<4096, 8>;
check_cuda(cudaFuncSetAttribute(
kernel,
cudaFuncAttributeMaxDynamicSharedMemorySize,
dyn_bytes),
"geqrf_4096_panel_smem_pack set dynamic smem");
kernel<<<batch, THREADS, dyn_bytes>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
v_panel.data_ptr<float>(),
t_panel.data_ptr<float>(),
batch,
kk,
ww);
check_cuda(cudaGetLastError(), "geqrf_4096_panel_smem_pack");
}
void geqrf_176_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width) {
geqrf_panel<176>(h, tau, t, k, width, "geqrf_176_panel_t");
}
void geqrf_352_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width) {
geqrf_panel<352>(h, tau, t, k, width, "geqrf_352_panel_t");
}
void geqrf_512_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width) {
geqrf_panel<512>(h, tau, t, k, width, "geqrf_512_panel_t");
}
void geqrf_1024_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width) {
geqrf_panel<1024>(h, tau, t, k, width, "geqrf_1024_panel_t");
}
void geqrf_2048_panel_t(torch::Tensor h, torch::Tensor tau, torch::Tensor t, int64_t k, int64_t width) {
geqrf_panel<2048>(h, tau, t, k, width, "geqrf_2048_panel_t");
}
void pack_v_panel(torch::Tensor h, torch::Tensor v, int64_t k, int64_t width) {
TORCH_CHECK(h.is_cuda() && v.is_cuda(), "pack_v_panel expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(v.scalar_type() == torch::kFloat32, "v must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(v.is_contiguous(), "v must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == h.size(2), "h must be batch x n x n");
TORCH_CHECK(v.dim() == 3, "v must be batch x rows x width");
const int batch = static_cast<int>(h.size(0));
const int n = static_cast<int>(h.size(1));
const int rows = static_cast<int>(v.size(1));
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(v.size(0) == batch, "v batch mismatch");
TORCH_CHECK(ww > 0 && ww <= MAX_PANEL && v.size(2) == ww, "invalid pack_v_panel width");
TORCH_CHECK(kk >= 0 && kk + ww <= n && rows == n - kk, "invalid pack_v_panel shape");
if (batch == 0) {
return;
}
const dim3 block(16, 16, 1);
const dim3 grid((ww + block.x - 1) / block.x, (rows + block.y - 1) / block.y, batch);
pack_v_panel_kernel<<<grid, block>>>(h.data_ptr<float>(), v.data_ptr<float>(), batch, n, rows, kk, ww);
check_cuda(cudaGetLastError(), "pack_v_panel");
}
void pack_v_panel_half(torch::Tensor h, torch::Tensor v, torch::Tensor vh, int64_t k, int64_t width) {
TORCH_CHECK(h.is_cuda() && v.is_cuda() && vh.is_cuda(), "pack_v_panel_half expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(v.scalar_type() == torch::kFloat32, "v must be float32");
TORCH_CHECK(vh.scalar_type() == torch::kFloat16, "vh must be float16");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(v.is_contiguous(), "v must be contiguous");
TORCH_CHECK(vh.is_contiguous(), "vh must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == h.size(2), "h must be batch x n x n");
TORCH_CHECK(v.dim() == 3 && vh.dim() == 3, "v outputs must be batch x rows x width");
const int batch = static_cast<int>(h.size(0));
const int n = static_cast<int>(h.size(1));
const int rows = static_cast<int>(v.size(1));
const int kk = static_cast<int>(k);
const int ww = static_cast<int>(width);
TORCH_CHECK(v.size(0) == batch && vh.size(0) == batch, "v batch mismatch");
TORCH_CHECK(vh.size(1) == rows && vh.size(2) == ww, "vh has wrong shape");
TORCH_CHECK(ww > 0 && ww <= MAX_PANEL && v.size(2) == ww, "invalid pack_v_panel_half width");
TORCH_CHECK(kk >= 0 && kk + ww <= n && rows == n - kk, "invalid pack_v_panel_half shape");
if (batch == 0) {
return;
}
const dim3 block(16, 16, 1);
const dim3 grid((ww + block.x - 1) / block.x, (rows + block.y - 1) / block.y, batch);
pack_v_panel_half_kernel<<<grid, block>>>(
h.data_ptr<float>(),
v.data_ptr<float>(),
reinterpret_cast<__half*>(vh.data_ptr<at::Half>()),
batch,
n,
rows,
kk,
ww);
check_cuda(cudaGetLastError(), "pack_v_panel_half");
}
void make_t_panel(torch::Tensor v, torch::Tensor tau, torch::Tensor t, int64_t width) {
TORCH_CHECK(v.is_cuda() && tau.is_cuda() && t.is_cuda(), "make_t_panel expects CUDA tensors");
TORCH_CHECK(v.scalar_type() == torch::kFloat32, "v must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(t.scalar_type() == torch::kFloat32, "t must be float32");
TORCH_CHECK(v.is_contiguous(), "v must be contiguous");
TORCH_CHECK(t.is_contiguous(), "t must be contiguous");
TORCH_CHECK(v.dim() == 3, "v must be batch x rows x width");
TORCH_CHECK(tau.dim() == 2, "tau must be batch x width");
TORCH_CHECK(t.dim() == 3, "t must be batch x width x width");
const int batch = static_cast<int>(v.size(0));
const int rows = static_cast<int>(v.size(1));
const int ww = static_cast<int>(width);
TORCH_CHECK(ww > 0 && ww <= MAX_PANEL, "invalid make_t_panel width");
TORCH_CHECK(v.size(2) == ww && tau.size(1) == ww && t.size(1) == ww && t.size(2) == ww, "make_t_panel shape mismatch");
if (batch == 0) {
return;
}
make_t_panel_kernel<<<batch, THREADS>>>(
v.data_ptr<float>(),
tau.data_ptr<float>(),
t.data_ptr<float>(),
batch,
rows,
ww,
static_cast<long long>(tau.stride(0)),
static_cast<long long>(tau.stride(1)));
check_cuda(cudaGetLastError(), "make_t_panel");
}
int64_t detect_zero_tail_rank_512(torch::Tensor data) {
TORCH_CHECK(data.is_cuda(), "detect_zero_tail_rank_512 expects CUDA tensor");
TORCH_CHECK(data.scalar_type() == torch::kFloat32, "data must be float32");
TORCH_CHECK(data.is_contiguous(), "data must be contiguous");
TORCH_CHECK(data.dim() == 3 && data.size(1) == 512 && data.size(2) == 512, "data has wrong shape");
const int batch = static_cast<int>(data.size(0));
if (batch == 0) {
return 0;
}
auto last = torch::empty({1}, data.options().dtype(torch::kInt32));
check_cuda(cudaMemset(last.data_ptr<int>(), 0xff, sizeof(int)), "detect_zero_tail_rank_512 memset");
detect_zero_tail_rank_512_kernel<<<512, THREADS>>>(
data.data_ptr<float>(),
batch,
last.data_ptr<int>());
check_cuda(cudaGetLastError(), "detect_zero_tail_rank_512");
auto last_cpu = last.cpu();
const int last_col = last_cpu.data_ptr<int>()[0];
const int rank = last_col + 1;
return rank >= 512 ? -1 : static_cast<int64_t>(rank);
}
int64_t detect_clustered_effective_cols_512(torch::Tensor data, double rel_threshold) {
TORCH_CHECK(data.is_cuda(), "detect_clustered_effective_cols_512 expects CUDA tensor");
TORCH_CHECK(data.scalar_type() == torch::kFloat32, "data must be float32");
TORCH_CHECK(data.is_contiguous(), "data must be contiguous");
TORCH_CHECK(data.dim() == 3 && data.size(1) == 512 && data.size(2) == 512, "data has wrong shape");
const int batch = static_cast<int>(data.size(0));
if (batch == 0) {
return 0;
}
auto col_max = torch::empty({512}, data.options());
auto effective = torch::empty({1}, data.options().dtype(torch::kInt32));
column_max_kernel<512><<<512, THREADS>>>(
data.data_ptr<float>(),
batch,
col_max.data_ptr<float>());
check_cuda(cudaGetLastError(), "detect_clustered_effective_cols_512 colmax");
clustered_effective_cols_512_kernel<<<1, THREADS>>>(
col_max.data_ptr<float>(),
static_cast<float>(rel_threshold),
effective.data_ptr<int>());
check_cuda(cudaGetLastError(), "detect_clustered_effective_cols_512 classify");
auto effective_cpu = effective.cpu();
return static_cast<int64_t>(effective_cpu.data_ptr<int>()[0]);
}
int64_t detect_nearrank_duplicate_rank_1024(torch::Tensor data, double rel_threshold) {
TORCH_CHECK(data.is_cuda(), "detect_nearrank_duplicate_rank_1024 expects CUDA tensor");
TORCH_CHECK(data.scalar_type() == torch::kFloat32, "data must be float32");
TORCH_CHECK(data.is_contiguous(), "data must be contiguous");
TORCH_CHECK(data.dim() == 3 && data.size(1) == 1024 && data.size(2) == 1024, "data has wrong shape");
const int batch = static_cast<int>(data.size(0));
if (batch == 0) {
return 0;
}
auto rank = torch::empty({1}, data.options().dtype(torch::kInt32));
const int sentinel = 1024;
check_cuda(cudaMemcpy(rank.data_ptr<int>(), &sentinel, sizeof(int), cudaMemcpyHostToDevice),
"detect_nearrank_duplicate_rank_1024 init");
detect_nearrank_duplicate_rank_1024_kernel<<<512, THREADS>>>(
data.data_ptr<float>(),
batch,
static_cast<float>(rel_threshold),
rank.data_ptr<int>());
check_cuda(cudaGetLastError(), "detect_nearrank_duplicate_rank_1024");
auto rank_cpu = rank.cpu();
const int value = rank_cpu.data_ptr<int>()[0];
return value >= 1024 ? -1 : static_cast<int64_t>(value);
}
void finalize_nearrank_tail_1024(torch::Tensor h, torch::Tensor tau, int64_t rank) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "finalize_nearrank_tail_1024 expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(tau.scalar_type() == torch::kFloat32, "tau must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(tau.is_contiguous(), "tau must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 1024 && h.size(2) == 1024, "h has wrong shape");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 1024, "tau has wrong shape");
const int batch = static_cast<int>(h.size(0));
const int rr = static_cast<int>(rank);
TORCH_CHECK(rr > 0 && rr < 1024, "invalid nearrank rank");
if (batch == 0) {
return;
}
const int tail = 1024 - rr;
const dim3 grid(tail, batch, 1);
finalize_nearrank_tail_1024_kernel<<<grid, THREADS>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
batch,
rr);
check_cuda(cudaGetLastError(), "finalize_nearrank_tail_1024");
}
template <int N>
void update_w16_hacc(torch::Tensor h, torch::Tensor v, torch::Tensor work, int64_t k, int64_t next_col, const char* name) {
TORCH_CHECK(h.is_cuda() && v.is_cuda() && work.is_cuda(), name, " expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(v.scalar_type() == torch::kFloat16, "v must be float16");
TORCH_CHECK(work.scalar_type() == torch::kFloat16, "work must be float16");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(v.is_contiguous(), "v must be contiguous");
TORCH_CHECK(work.is_contiguous(), "work must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == N && h.size(2) == N, "h has wrong shape");
TORCH_CHECK(v.dim() == 3 && v.size(2) == 16, "v must be batch x rows x 16");
TORCH_CHECK(work.dim() == 3 && work.size(1) == 16, "work must be batch x 16 x cols");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int nc = static_cast<int>(next_col);
TORCH_CHECK(kk >= 0 && kk + 16 <= N, "invalid panel offset");
TORCH_CHECK(nc >= kk + 16 && nc <= N, "invalid next_col");
TORCH_CHECK(v.size(0) == batch && v.size(1) == N - kk, "v has wrong shape");
TORCH_CHECK(work.size(0) == batch && work.size(2) == N - nc, "work has wrong shape");
if (batch == 0 || nc >= N) {
return;
}
constexpr int TILE = 16;
constexpr int WARPS = 8;
const int tile_cols = (N - nc + TILE - 1) / TILE;
const dim3 block(32 * WARPS, 1, 1);
const dim3 grid((tile_cols + WARPS - 1) / WARPS, (N - kk + TILE - 1) / TILE, batch);
update_w16_hmma_kernel<N><<<grid, block>>>(
h.data_ptr<float>(),
reinterpret_cast<const __half*>(v.data_ptr<at::Half>()),
reinterpret_cast<const __half*>(work.data_ptr<at::Half>()),
batch,
kk,
nc);
check_cuda(cudaGetLastError(), name);
}
void update_512_w16_hacc(torch::Tensor h, torch::Tensor v, torch::Tensor work, int64_t k, int64_t next_col) {
update_w16_hacc<512>(h, v, work, k, next_col, "update_512_w16_hacc");
}
void update_1024_w16_hacc(torch::Tensor h, torch::Tensor v, torch::Tensor work, int64_t k, int64_t next_col) {
update_w16_hacc<1024>(h, v, work, k, next_col, "update_1024_w16_hacc");
}
template <int N, int W>
void update_n_w_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col, const char* name) {
TORCH_CHECK(h.is_cuda() && v.is_cuda() && work.is_cuda() && workspace.is_cuda(), name, " expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(v.scalar_type() == torch::kFloat16, "v must be float16");
TORCH_CHECK(work.scalar_type() == torch::kFloat16, "work must be float16");
TORCH_CHECK(workspace.scalar_type() == torch::kUInt8, "workspace must be uint8");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(v.is_contiguous(), "v must be contiguous");
TORCH_CHECK(work.is_contiguous(), "work must be contiguous");
TORCH_CHECK(workspace.is_contiguous(), "workspace must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == N && h.size(2) == N, "h has wrong shape");
TORCH_CHECK(v.dim() == 3 && v.size(2) == W, "v has wrong width");
TORCH_CHECK(work.dim() == 3 && work.size(1) == W, "work has wrong width");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int nc = static_cast<int>(next_col);
TORCH_CHECK(kk >= 0 && kk + W <= N, "invalid panel offset");
TORCH_CHECK(nc >= kk + W && nc <= N, "invalid next_col");
TORCH_CHECK(v.size(0) == batch && v.size(1) == N - kk, "v has wrong shape");
TORCH_CHECK(work.size(0) == batch && work.size(2) == N - nc, "work has wrong shape");
if (batch == 0 || nc >= N) {
return;
}
// #if QRV2_HAS_CUTLASS
const int rows = N - kk;
const int cols = N - nc;
Cutlass512ElementA const* a_ptr = reinterpret_cast<Cutlass512ElementA const*>(v.data_ptr<at::Half>());
Cutlass512ElementB const* b_ptr = reinterpret_cast<Cutlass512ElementB const*>(work.data_ptr<at::Half>());
Cutlass512ElementC* c_ptr = h.data_ptr<float>() + static_cast<long long>(kk) * N + nc;
const int64_t batch_stride_a = static_cast<int64_t>(rows) * W;
const int64_t batch_stride_b = static_cast<int64_t>(W) * cols;
constexpr long long batch_stride_c = static_cast<long long>(N) * N;
auto stride_a = cute::make_stride(static_cast<int64_t>(W), cute::Int<1>{}, batch_stride_a);
auto stride_b = cute::make_stride(cute::Int<1>{}, static_cast<int64_t>(cols), batch_stride_b);
auto stride_c = cute::make_stride(static_cast<int64_t>(N), cute::Int<1>{}, static_cast<int64_t>(batch_stride_c));
typename Cutlass512Gemm::Arguments args;
args.mode = cutlass::gemm::GemmUniversalMode::kBatched;
args.problem_shape = cute::make_shape(rows, cols, W, batch);
args.mainloop.ptr_A = a_ptr;
args.mainloop.dA = stride_a;
args.mainloop.ptr_B = b_ptr;
args.mainloop.dB = stride_b;
args.epilogue.thread = {Cutlass512Accumulator(-1.0f), Cutlass512Accumulator(1.0f)};
args.epilogue.ptr_C = c_ptr;
args.epilogue.dC = stride_c;
args.epilogue.ptr_D = c_ptr;
args.epilogue.dD = stride_c;
Cutlass512Gemm gemm_op;
cutlass::Status status = gemm_op.can_implement(args);
TORCH_CHECK(status == cutlass::Status::kSuccess, name, " cannot implement problem");
const size_t workspace_size = gemm_op.get_workspace_size(args);
TORCH_CHECK(static_cast<size_t>(workspace.numel()) >= workspace_size, name, " workspace too small");
status = gemm_op(args, workspace.data_ptr());
TORCH_CHECK(status == cutlass::Status::kSuccess, name, " failed");
check_cuda(cudaGetLastError(), name);
// #else
// (void)workspace;
// update_512_w16_hacc(h, v, work, k, next_col);
// #endif
}
void update_512_w16_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col) {
update_n_w_cutlass<512, 16>(h, v, work, workspace, k, next_col, "update_512_w16_cutlass");
}
void update_512_w32_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col) {
update_n_w_cutlass<512, 32>(h, v, work, workspace, k, next_col, "update_512_w32_cutlass");
}
void update_1024_w32_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col) {
update_n_w_cutlass<1024, 32>(h, v, work, workspace, k, next_col, "update_1024_w32_cutlass");
}
void update_2048_w64_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col) {
update_n_w_cutlass<2048, 64>(h, v, work, workspace, k, next_col, "update_2048_w64_cutlass");
}
void update_4096_w64_cutlass(torch::Tensor h, torch::Tensor v, torch::Tensor work, torch::Tensor workspace, int64_t k, int64_t next_col) {
update_n_w_cutlass<4096, 64>(h, v, work, workspace, k, next_col, "update_4096_w64_cutlass");
}
void update_512_w16_fused(torch::Tensor h, torch::Tensor v, torch::Tensor t, int64_t k, int64_t next_col) {
TORCH_CHECK(h.is_cuda() && v.is_cuda() && t.is_cuda(), "update_512_w16_fused expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(v.scalar_type() == torch::kFloat32, "v must be float32");
TORCH_CHECK(t.scalar_type() == torch::kFloat32, "t must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(v.is_contiguous(), "v must be contiguous");
TORCH_CHECK(t.is_contiguous(), "t must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 512 && h.size(2) == 512, "h has wrong shape");
TORCH_CHECK(v.dim() == 3 && v.size(2) == 16, "v must be batch x rows x 16");
TORCH_CHECK(t.dim() == 3 && t.size(1) == 16 && t.size(2) == 16, "t must be batch x 16 x 16");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int nc = static_cast<int>(next_col);
TORCH_CHECK(kk >= 0 && kk + 16 <= 512, "invalid panel offset");
TORCH_CHECK(nc == kk + 16 && nc <= 512, "invalid next_col");
TORCH_CHECK(v.size(0) == batch && v.size(1) == 512 - kk, "v has wrong shape");
TORCH_CHECK(t.size(0) == batch, "t has wrong shape");
if (batch == 0 || nc >= 512) {
return;
}
constexpr int TILE_COLS = 16;
const int cols = 512 - nc;
const dim3 block(256, 1, 1);
const dim3 grid((cols + TILE_COLS - 1) / TILE_COLS, batch, 1);
update_512_w16_fused_kernel<<<grid, block>>>(
h.data_ptr<float>(),
v.data_ptr<float>(),
t.data_ptr<float>(),
batch,
kk,
nc);
check_cuda(cudaGetLastError(), "update_512_w16_fused");
}
void update_2048_w4(torch::Tensor h, torch::Tensor v, torch::Tensor t, int64_t k, int64_t next_col) {
TORCH_CHECK(h.is_cuda() && v.is_cuda() && t.is_cuda(), "update_2048_w4 expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(v.scalar_type() == torch::kFloat32, "v must be float32");
TORCH_CHECK(t.scalar_type() == torch::kFloat32, "t must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(v.is_contiguous(), "v must be contiguous");
TORCH_CHECK(t.is_contiguous(), "t must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 2048 && h.size(2) == 2048, "h has wrong shape");
TORCH_CHECK(v.dim() == 3 && v.size(2) == 4, "v must be batch x rows x 4");
TORCH_CHECK(t.dim() == 3 && t.size(1) == 4 && t.size(2) == 4, "t must be batch x 4 x 4");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int nc = static_cast<int>(next_col);
TORCH_CHECK(kk >= 0 && kk + 4 <= 2048, "invalid panel offset");
TORCH_CHECK(nc == kk + 4 && nc <= 2048, "invalid next_col");
TORCH_CHECK(v.size(0) == batch && v.size(1) == 2048 - kk, "v has wrong shape");
TORCH_CHECK(t.size(0) == batch, "t batch mismatch");
if (batch == 0 || nc >= 2048) {
return;
}
const dim3 grid(2048 - nc, batch, 1);
update_2048_w4_kernel<<<grid, THREADS>>>(
h.data_ptr<float>(),
v.data_ptr<float>(),
t.data_ptr<float>(),
batch,
kk,
nc);
check_cuda(cudaGetLastError(), "update_2048_w4");
}
template <int W>
void update_2048_w_tile8(torch::Tensor h, torch::Tensor v, torch::Tensor t, int64_t k, int64_t next_col, const char* name) {
TORCH_CHECK(h.is_cuda() && v.is_cuda() && t.is_cuda(), name, " expects CUDA tensors");
TORCH_CHECK(h.scalar_type() == torch::kFloat32, "h must be float32");
TORCH_CHECK(v.scalar_type() == torch::kFloat32, "v must be float32");
TORCH_CHECK(t.scalar_type() == torch::kFloat32, "t must be float32");
TORCH_CHECK(h.is_contiguous(), "h must be contiguous");
TORCH_CHECK(v.is_contiguous(), "v must be contiguous");
TORCH_CHECK(t.is_contiguous(), "t must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 2048 && h.size(2) == 2048, "h has wrong shape");
TORCH_CHECK(v.dim() == 3 && v.size(2) == W, "v has wrong width");
TORCH_CHECK(t.dim() == 3 && t.size(1) == W && t.size(2) == W, "t has wrong width");
const int batch = static_cast<int>(h.size(0));
const int kk = static_cast<int>(k);
const int nc = static_cast<int>(next_col);
TORCH_CHECK(kk >= 0 && kk + W <= 2048, "invalid panel offset");
TORCH_CHECK(nc == kk + W && nc <= 2048, "invalid next_col");
TORCH_CHECK(v.size(0) == batch && v.size(1) == 2048 - kk, "v has wrong shape");
TORCH_CHECK(t.size(0) == batch, "t batch mismatch");
if (batch == 0 || nc >= 2048) {
return;
}
constexpr int TILE_COLS = 8;
const dim3 block(32 * TILE_COLS, 1, 1);
const dim3 grid((2048 - nc + TILE_COLS - 1) / TILE_COLS, batch, 1);
update_2048_w_tile8_kernel<W><<<grid, block>>>(
h.data_ptr<float>(),
v.data_ptr<float>(),
t.data_ptr<float>(),
batch,
kk,
nc);
check_cuda(cudaGetLastError(), name);
}
void update_2048_w4_tile8(torch::Tensor h, torch::Tensor v, torch::Tensor t, int64_t k, int64_t next_col) {
update_2048_w_tile8<4>(h, v, t, k, next_col, "update_2048_w4_tile8");
}
void update_2048_w8_tile8(torch::Tensor h, torch::Tensor v, torch::Tensor t, int64_t k, int64_t next_col) {
update_2048_w_tile8<8>(h, v, t, k, next_col, "update_2048_w8_tile8");
}
__global__ void __launch_bounds__(THREADS) merge_p8_tree_32_kernel(const float* __restrict__ v,
const float* __restrict__ t_panels,
float* __restrict__ t_out,
int batch,
int rows) {
const int b = blockIdx.x;
const int tid = threadIdx.x;
if (b >= batch) {
return;
}
__shared__ float t0[64];
__shared__ float t1[64];
__shared__ float t2[64];
__shared__ float t3[64];
__shared__ float c01[64];
__shared__ float c23[64];
__shared__ float left16[256];
__shared__ float right16[256];
__shared__ float c16[256];
const float* vb = v + static_cast<long long>(b) * rows * 32;
float* out = t_out + static_cast<long long>(b) * 32 * 32;
for (int idx = tid; idx < 64; idx += blockDim.x) {
t0[idx] = t_panels[(static_cast<long long>(0) * batch + b) * 64 + idx];
t1[idx] = t_panels[(static_cast<long long>(1) * batch + b) * 64 + idx];
t2[idx] = t_panels[(static_cast<long long>(2) * batch + b) * 64 + idx];
t3[idx] = t_panels[(static_cast<long long>(3) * batch + b) * 64 + idx];
}
for (int idx = tid; idx < 256; idx += blockDim.x) {
left16[idx] = 0.0f;
right16[idx] = 0.0f;
}
__syncthreads();
for (int idx = tid; idx < 64; idx += blockDim.x) {
const int i = idx >> 3;
const int j = idx & 7;
float s01 = 0.0f;
float s23 = 0.0f;
for (int r = 0; r < rows; ++r) {
const float* row = vb + static_cast<long long>(r) * 32;
s01 += row[i] * row[8 + j];
s23 += row[16 + i] * row[24 + j];
}
c01[idx] = s01;
c23[idx] = s23;
}
__syncthreads();
for (int idx = tid; idx < 64; idx += blockDim.x) {
const int i = idx >> 3;
const int j = idx & 7;
left16[i * 16 + j] = t0[idx];
left16[(8 + i) * 16 + 8 + j] = t1[idx];
right16[i * 16 + j] = t2[idx];
right16[(8 + i) * 16 + 8 + j] = t3[idx];
float acc01 = 0.0f;
float acc23 = 0.0f;
#pragma unroll
for (int q = 0; q < 8; ++q) {
#pragma unroll
for (int r = 0; r < 8; ++r) {
acc01 += t0[i * 8 + q] * c01[q * 8 + r] * t1[r * 8 + j];
acc23 += t2[i * 8 + q] * c23[q * 8 + r] * t3[r * 8 + j];
}
}
left16[i * 16 + 8 + j] = -acc01;
right16[i * 16 + 8 + j] = -acc23;
}
__syncthreads();
for (int idx = tid; idx < 256; idx += blockDim.x) {
const int i = idx >> 4;
const int j = idx & 15;
float sum = 0.0f;
for (int r = 0; r < rows; ++r) {
const float* row = vb + static_cast<long long>(r) * 32;
sum += row[i] * row[16 + j];
}
c16[idx] = sum;
}
__syncthreads();
for (int idx = tid; idx < 256; idx += blockDim.x) {
const int i = idx >> 4;
const int j = idx & 15;
out[i * 32 + j] = left16[idx];
out[(16 + i) * 32 + j] = 0.0f;
out[(16 + i) * 32 + 16 + j] = right16[idx];
float acc = 0.0f;
#pragma unroll
for (int q = 0; q < 16; ++q) {
#pragma unroll
for (int r = 0; r < 16; ++r) {
acc += left16[i * 16 + q] * c16[q * 16 + r] * right16[r * 16 + j];
}
}
out[i * 32 + 16 + j] = -acc;
}
}
void merge_p8_tree_32(torch::Tensor v_block, torch::Tensor t_panels, torch::Tensor t_out) {
TORCH_CHECK(v_block.is_cuda() && t_panels.is_cuda() && t_out.is_cuda(), "merge_p8_tree_32 expects CUDA tensors");
TORCH_CHECK(v_block.scalar_type() == torch::kFloat32, "v_block must be float32");
TORCH_CHECK(t_panels.scalar_type() == torch::kFloat32, "t_panels must be float32");
TORCH_CHECK(t_out.scalar_type() == torch::kFloat32, "t_out must be float32");
TORCH_CHECK(v_block.is_contiguous(), "v_block must be contiguous");
TORCH_CHECK(t_panels.is_contiguous(), "t_panels must be contiguous");
TORCH_CHECK(t_out.is_contiguous(), "t_out must be contiguous");
TORCH_CHECK(v_block.dim() == 3 && v_block.size(2) == 32, "v_block must be batch x rows x 32");
TORCH_CHECK(t_panels.dim() == 4 && t_panels.size(0) >= 4 && t_panels.size(2) == 8 && t_panels.size(3) == 8, "t_panels must be at least 4 x batch x 8 x 8");
TORCH_CHECK(t_out.dim() == 3 && t_out.size(1) == 32 && t_out.size(2) == 32, "t_out must be batch x 32 x 32");
const int batch = static_cast<int>(v_block.size(0));
const int rows = static_cast<int>(v_block.size(1));
TORCH_CHECK(t_panels.size(1) == batch && t_out.size(0) == batch, "merge_p8_tree_32 batch mismatch");
if (batch == 0) {
return;
}
merge_p8_tree_32_kernel<<<batch, THREADS>>>(
v_block.data_ptr<float>(),
t_panels.data_ptr<float>(),
t_out.data_ptr<float>(),
batch,
rows);
check_cuda(cudaGetLastError(), "merge_p8_tree_32");
}
inline torch::Tensor view_workspace3(torch::Tensor storage, int batch, int rows, int width) {
const int64_t numel = static_cast<int64_t>(batch) * rows * width;
return storage.narrow(0, 0, numel).view({
static_cast<int64_t>(batch),
static_cast<int64_t>(rows),
static_cast<int64_t>(width),
});
}
inline void apply_trailing_update_cpp(torch::Tensor trailing,
torch::Tensor v,
torch::Tensor t,
torch::Tensor work1,
torch::Tensor work2) {
at::bmm_out(work1, v.transpose(1, 2), trailing);
at::bmm_out(work2, t.transpose(1, 2), work1);
at::baddbmm_out(trailing, trailing, v, work2, 1.0, -1.0);
}
void qr_176_panel8_driver(torch::Tensor h,
torch::Tensor tau,
torch::Tensor v_storage,
torch::Tensor t_workspace,
torch::Tensor work1_storage,
torch::Tensor work2_storage) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "qr_176_panel8_driver expects CUDA tensors");
TORCH_CHECK(v_storage.is_cuda() && t_workspace.is_cuda() && work1_storage.is_cuda() && work2_storage.is_cuda(), "workspaces must be CUDA");
TORCH_CHECK(h.scalar_type() == torch::kFloat32 && tau.scalar_type() == torch::kFloat32, "h/tau must be float32");
TORCH_CHECK(v_storage.scalar_type() == torch::kFloat32 && t_workspace.scalar_type() == torch::kFloat32, "V/T workspaces must be float32");
TORCH_CHECK(work1_storage.scalar_type() == torch::kFloat32 && work2_storage.scalar_type() == torch::kFloat32, "update workspaces must be float32");
TORCH_CHECK(h.is_contiguous() && tau.is_contiguous(), "h/tau must be contiguous");
TORCH_CHECK(v_storage.is_contiguous() && t_workspace.is_contiguous() && work1_storage.is_contiguous() && work2_storage.is_contiguous(), "workspaces must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 176 && h.size(2) == 176, "h must be batch x 176 x 176");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 176, "tau must be batch x 176");
TORCH_CHECK(t_workspace.dim() == 3 && t_workspace.size(1) == 8 && t_workspace.size(2) == 8, "t workspace must be batch x 8 x 8");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(tau.size(0) == batch && t_workspace.size(0) == batch, "batch mismatch");
TORCH_CHECK(v_storage.numel() >= static_cast<int64_t>(batch) * 176 * 8, "v workspace too small");
TORCH_CHECK(work1_storage.numel() >= static_cast<int64_t>(batch) * 8 * 176, "work1 workspace too small");
TORCH_CHECK(work2_storage.numel() >= static_cast<int64_t>(batch) * 8 * 176, "work2 workspace too small");
if (batch == 0) {
return;
}
constexpr int panel = 8;
for (int k = 0; k < 176; k += panel) {
const int next_col = k + panel;
if (next_col >= 176) {
geqrf_176_panel_smem_t(h, tau, t_workspace, k, panel);
continue;
}
auto v = view_workspace3(v_storage, batch, 176 - k, panel);
geqrf_176_panel_smem_pack_t(h, tau, v, t_workspace, k, panel);
auto trailing = h.narrow(1, k, 176 - k).narrow(2, next_col, 176 - next_col);
const int cols = 176 - next_col;
auto work1 = view_workspace3(work1_storage, batch, panel, cols);
auto work2 = view_workspace3(work2_storage, batch, panel, cols);
apply_trailing_update_cpp(trailing, v, t_workspace, work1, work2);
}
}
inline void apply_512_lowp_update_cpp(torch::Tensor h,
torch::Tensor trailing,
torch::Tensor v_block_h,
torch::Tensor v_block,
torch::Tensor t_block,
torch::Tensor work1,
torch::Tensor work2,
torch::Tensor work_h,
torch::Tensor split_v_h_storage,
torch::Tensor split_work_h_storage,
torch::Tensor cutlass_workspace,
int batch,
int k,
int next_col,
int cols) {
at::bmm_out(work1, v_block.transpose(1, 2), trailing);
at::bmm_out(work2, t_block.transpose(1, 2), work1);
work_h.copy_(work2);
update_512_w32_cutlass(h, v_block_h, work_h, cutlass_workspace, k, next_col);
}
inline void apply_512_w32_active_update_cpp(torch::Tensor h,
torch::Tensor v_block,
torch::Tensor t_block,
torch::Tensor active_cols,
int batch,
int k,
int next_col) {
constexpr int tile_cols = 8;
const int cols = 512 - next_col;
if (cols <= 0) {
return;
}
const dim3 grid((cols + tile_cols - 1) / tile_cols, batch, 1);
update_512_w32_active_kernel<<<grid, THREADS>>>(
h.data_ptr<float>(),
v_block.data_ptr<float>(),
t_block.data_ptr<float>(),
active_cols.data_ptr<int>(),
batch,
k,
next_col);
check_cuda(cudaGetLastError(), "update_512_w32_active");
}
inline void apply_512_w16_active_wmma_update_cpp(torch::Tensor h,
torch::Tensor trailing,
torch::Tensor v_block_h,
torch::Tensor v_block,
torch::Tensor t_block,
torch::Tensor work1,
torch::Tensor work2,
torch::Tensor work_h,
torch::Tensor split_v_h_storage,
torch::Tensor split_work_h_storage,
torch::Tensor active_cols,
int batch,
int k,
int next_col,
int cols) {
at::bmm_out(work1, v_block.transpose(1, 2), trailing);
at::bmm_out(work2, t_block.transpose(1, 2), work1);
work_h.copy_(work2);
auto v_h16 = view_workspace3(split_v_h_storage, batch, 512 - k, 16);
auto work_h16 = view_workspace3(split_work_h_storage, batch, 16, cols);
const dim3 grid((cols + 15) / 16, (512 - k + 15) / 16, batch);
for (int offset = 0; offset < 32; offset += 16) {
v_h16.copy_(v_block_h.narrow(2, offset, 16));
work_h16.copy_(work_h.narrow(1, offset, 16));
update_512_w16_active_wmma_kernel<<<grid, THREADS>>>(
h.data_ptr<float>(),
reinterpret_cast<const __half*>(v_h16.data_ptr<at::Half>()),
reinterpret_cast<const __half*>(work_h16.data_ptr<at::Half>()),
active_cols.data_ptr<int>(),
batch,
k,
next_col);
check_cuda(cudaGetLastError(), "update_512_w16_active_wmma");
}
}
inline void apply_512_w16_active_grouped_cutlass_update_cpp(torch::Tensor h,
torch::Tensor trailing,
torch::Tensor v_block_h,
torch::Tensor v_block,
torch::Tensor t_block,
torch::Tensor work1,
torch::Tensor work2,
torch::Tensor work_h,
torch::Tensor split_v_h_storage,
torch::Tensor split_work_h_storage,
torch::Tensor active_cols,
torch::Tensor cutlass_workspace,
torch::Tensor problem_sizes,
torch::Tensor ptr_a,
torch::Tensor ptr_b,
torch::Tensor ptr_c,
torch::Tensor ptr_d,
torch::Tensor lda,
torch::Tensor ldb,
torch::Tensor ldc,
torch::Tensor ldd,
int batch,
int k,
int next_col,
int cols) {
at::bmm_out(work1, v_block.transpose(1, 2), trailing);
at::bmm_out(work2, t_block.transpose(1, 2), work1);
work_h.copy_(work2);
for (int offset = 0; offset < 32; offset += 16) {
const __half* v_ptr = reinterpret_cast<const __half*>(v_block_h.data_ptr<at::Half>()) + offset;
const __half* work_ptr = reinterpret_cast<const __half*>(work_h.data_ptr<at::Half>()) + static_cast<long long>(offset) * cols;
setup_512_w16_active_grouped_kernel<<<(batch + 255) / 256, 256>>>(
v_ptr,
work_ptr,
h.data_ptr<float>(),
active_cols.data_ptr<int>(),
reinterpret_cast<cutlass::gemm::GemmCoord*>(problem_sizes.data_ptr<int>()),
reinterpret_cast<Cutlass512ElementA**>(ptr_a.data_ptr<int64_t>()),
reinterpret_cast<Cutlass512ElementB**>(ptr_b.data_ptr<int64_t>()),
reinterpret_cast<Cutlass512ElementC**>(ptr_c.data_ptr<int64_t>()),
reinterpret_cast<Cutlass512ElementC**>(ptr_d.data_ptr<int64_t>()),
lda.data_ptr<int64_t>(),
ldb.data_ptr<int64_t>(),
ldc.data_ptr<int64_t>(),
ldd.data_ptr<int64_t>(),
batch,
k,
next_col,
cols,
32,
cols);
check_cuda(cudaGetLastError(), "setup_512_w16_active_grouped");
typename Cutlass512GroupedGemm::Arguments args(
reinterpret_cast<cutlass::gemm::GemmCoord*>(problem_sizes.data_ptr<int>()),
batch,
batch * ((512 - k + 63) / 64) * ((cols + 63) / 64),
{Cutlass512Accumulator(-1.0f), Cutlass512Accumulator(1.0f)},
reinterpret_cast<Cutlass512ElementA**>(ptr_a.data_ptr<int64_t>()),
reinterpret_cast<Cutlass512ElementB**>(ptr_b.data_ptr<int64_t>()),
reinterpret_cast<Cutlass512ElementC**>(ptr_c.data_ptr<int64_t>()),
reinterpret_cast<Cutlass512ElementC**>(ptr_d.data_ptr<int64_t>()),
lda.data_ptr<int64_t>(),
ldb.data_ptr<int64_t>(),
ldc.data_ptr<int64_t>(),
ldd.data_ptr<int64_t>());
Cutlass512GroupedGemm gemm_op;
cutlass::Status status = gemm_op(args, cutlass_workspace.data_ptr());
TORCH_CHECK(status == cutlass::Status::kSuccess, "active grouped cutlass failed");
check_cuda(cudaGetLastError(), "active grouped cutlass");
}
}
void qr_512_superpanel32_active_driver(torch::Tensor h,
torch::Tensor tau,
torch::Tensor v_panel_storage,
torch::Tensor v_block_storage,
torch::Tensor v_block_h_storage,
torch::Tensor t_panel_workspace,
torch::Tensor t_block_workspace,
torch::Tensor local_work1_storage,
torch::Tensor local_work2_storage,
torch::Tensor work1_storage,
torch::Tensor work2_storage,
torch::Tensor work_h_storage,
torch::Tensor split_v_h_storage,
torch::Tensor split_work_h_storage,
torch::Tensor cutlass_workspace,
torch::Tensor active_problem_sizes,
torch::Tensor active_ptr_a,
torch::Tensor active_ptr_b,
torch::Tensor active_ptr_c,
torch::Tensor active_ptr_d,
torch::Tensor active_lda,
torch::Tensor active_ldb,
torch::Tensor active_ldc,
torch::Tensor active_ldd) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "qr_512_superpanel32_active_driver expects CUDA tensors");
TORCH_CHECK(v_panel_storage.is_cuda() && v_block_storage.is_cuda() && v_block_h_storage.is_cuda(), "V workspaces must be CUDA");
TORCH_CHECK(t_panel_workspace.is_cuda() && t_block_workspace.is_cuda(), "T workspaces must be CUDA");
TORCH_CHECK(local_work1_storage.is_cuda() && local_work2_storage.is_cuda(), "local workspaces must be CUDA");
TORCH_CHECK(work1_storage.is_cuda() && work2_storage.is_cuda() && work_h_storage.is_cuda(), "update workspaces must be CUDA");
TORCH_CHECK(split_v_h_storage.is_cuda() && split_work_h_storage.is_cuda() && cutlass_workspace.is_cuda(), "lowp workspaces must be CUDA");
TORCH_CHECK(active_problem_sizes.is_cuda() && active_ptr_a.is_cuda() && active_ptr_b.is_cuda() && active_ptr_c.is_cuda() && active_ptr_d.is_cuda(), "active pointer workspaces must be CUDA");
TORCH_CHECK(active_lda.is_cuda() && active_ldb.is_cuda() && active_ldc.is_cuda() && active_ldd.is_cuda(), "active stride workspaces must be CUDA");
TORCH_CHECK(h.scalar_type() == torch::kFloat32 && tau.scalar_type() == torch::kFloat32, "h/tau must be float32");
TORCH_CHECK(v_panel_storage.scalar_type() == torch::kFloat32 && v_block_storage.scalar_type() == torch::kFloat32, "V workspaces must be float32");
TORCH_CHECK(v_block_h_storage.scalar_type() == torch::kFloat16, "v_block_h_storage must be float16");
TORCH_CHECK(t_panel_workspace.scalar_type() == torch::kFloat32 && t_block_workspace.scalar_type() == torch::kFloat32, "T workspaces must be float32");
TORCH_CHECK(local_work1_storage.scalar_type() == torch::kFloat32 && local_work2_storage.scalar_type() == torch::kFloat32, "local workspaces must be float32");
TORCH_CHECK(work1_storage.scalar_type() == torch::kFloat32 && work2_storage.scalar_type() == torch::kFloat32, "update workspaces must be float32");
TORCH_CHECK(work_h_storage.scalar_type() == torch::kFloat16 && split_v_h_storage.scalar_type() == torch::kFloat16 && split_work_h_storage.scalar_type() == torch::kFloat16, "half workspaces must be float16");
TORCH_CHECK(cutlass_workspace.scalar_type() == torch::kUInt8, "cutlass workspace must be uint8");
TORCH_CHECK(active_problem_sizes.scalar_type() == torch::kInt32, "active_problem_sizes must be int32");
TORCH_CHECK(active_ptr_a.scalar_type() == torch::kInt64 && active_ptr_b.scalar_type() == torch::kInt64 && active_ptr_c.scalar_type() == torch::kInt64 && active_ptr_d.scalar_type() == torch::kInt64, "active pointer workspaces must be int64");
TORCH_CHECK(active_lda.scalar_type() == torch::kInt64 && active_ldb.scalar_type() == torch::kInt64 && active_ldc.scalar_type() == torch::kInt64 && active_ldd.scalar_type() == torch::kInt64, "active stride workspaces must be int64");
TORCH_CHECK(h.is_contiguous() && tau.is_contiguous(), "h/tau must be contiguous");
TORCH_CHECK(v_panel_storage.is_contiguous() && v_block_storage.is_contiguous() && v_block_h_storage.is_contiguous(), "V workspaces must be contiguous");
TORCH_CHECK(t_panel_workspace.is_contiguous() && t_block_workspace.is_contiguous(), "T workspaces must be contiguous");
TORCH_CHECK(local_work1_storage.is_contiguous() && local_work2_storage.is_contiguous(), "local workspaces must be contiguous");
TORCH_CHECK(work1_storage.is_contiguous() && work2_storage.is_contiguous() && work_h_storage.is_contiguous(), "update workspaces must be contiguous");
TORCH_CHECK(split_v_h_storage.is_contiguous() && split_work_h_storage.is_contiguous() && cutlass_workspace.is_contiguous(), "lowp workspaces must be contiguous");
TORCH_CHECK(active_problem_sizes.is_contiguous() && active_ptr_a.is_contiguous() && active_ptr_b.is_contiguous() && active_ptr_c.is_contiguous() && active_ptr_d.is_contiguous(), "active pointer workspaces must be contiguous");
TORCH_CHECK(active_lda.is_contiguous() && active_ldb.is_contiguous() && active_ldc.is_contiguous() && active_ldd.is_contiguous(), "active stride workspaces must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 512 && h.size(2) == 512, "h must be batch x 512 x 512");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 512, "tau must be batch x 512");
TORCH_CHECK(t_panel_workspace.dim() == 4 && t_panel_workspace.size(0) >= 4 && t_panel_workspace.size(2) == 8 && t_panel_workspace.size(3) == 8, "t panel workspace has wrong shape");
TORCH_CHECK(t_block_workspace.dim() == 3 && t_block_workspace.size(1) == 32 && t_block_workspace.size(2) == 32, "t block workspace has wrong shape");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(tau.size(0) == batch && t_panel_workspace.size(1) == batch && t_block_workspace.size(0) == batch, "batch mismatch");
TORCH_CHECK(active_problem_sizes.numel() >= static_cast<int64_t>(batch) * 3, "active_problem_sizes too small");
TORCH_CHECK(active_ptr_a.numel() >= batch && active_ptr_b.numel() >= batch && active_ptr_c.numel() >= batch && active_ptr_d.numel() >= batch, "active pointer workspace too small");
TORCH_CHECK(active_lda.numel() >= batch && active_ldb.numel() >= batch && active_ldc.numel() >= batch && active_ldd.numel() >= batch, "active stride workspace too small");
if (batch == 0) {
return;
}
torch::Tensor active_cols = torch::empty({batch}, h.options().dtype(torch::kInt32));
classify_zero_tail_active_cols_512_kernel<<<batch, THREADS>>>(
h.data_ptr<float>(),
batch,
active_cols.data_ptr<int>());
check_cuda(cudaGetLastError(), "classify_zero_tail_active_cols_512");
constexpr int panel = 8;
constexpr int superpanel = 32;
constexpr int lowp_min_trailing_cols = 256;
constexpr bool use_grouped_late_update = false;
#pragma unroll
for (int k = 0; k < 512; k += superpanel) {
const int block_end = k + superpanel;
const bool has_trailing = block_end < 512;
const bool use_lowp_block = has_trailing && (512 - block_end) >= lowp_min_trailing_cols;
auto v_block = view_workspace3(v_block_storage, batch, 512 - k, superpanel);
auto v_block_h = view_workspace3(v_block_h_storage, batch, 512 - k, superpanel);
#pragma unroll
for (int kk = k; kk < block_end; kk += panel) {
const int next_col = kk + panel;
auto v = view_workspace3(v_panel_storage, batch, 512 - kk, panel);
auto t = t_panel_workspace.select(0, (kk - k) / panel);
if (has_trailing) {
geqrf_512_panel_smem_pack_h(h, tau, kk, panel, v, v_block, v_block_h, t, k, kk - k);
} else {
geqrf_512_panel_smem(h, tau, kk, panel);
if (next_col < block_end) {
pack_v_panel(h, v, kk, panel);
make_t_panel(v, tau.narrow(1, kk, panel), t, panel);
}
}
if (next_col < block_end) {
auto local_trailing = h.narrow(1, kk, 512 - kk).narrow(2, next_col, block_end - next_col);
auto local_work1 = view_workspace3(local_work1_storage, batch, panel, block_end - next_col);
auto local_work2 = view_workspace3(local_work2_storage, batch, panel, block_end - next_col);
apply_trailing_update_cpp(local_trailing, v, t, local_work1, local_work2);
}
}
if (!has_trailing) {
continue;
}
merge_p8_tree_32(v_block, t_panel_workspace, t_block_workspace);
auto trailing = h.narrow(1, k, 512 - k).narrow(2, block_end, 512 - block_end);
const int cols = 512 - block_end;
auto work1 = view_workspace3(work1_storage, batch, superpanel, cols);
auto work2 = view_workspace3(work2_storage, batch, superpanel, cols);
if constexpr (use_grouped_late_update) {
auto work_h = view_workspace3(work_h_storage, batch, superpanel, cols);
apply_512_w16_active_grouped_cutlass_update_cpp(
h,
trailing,
v_block_h,
v_block,
t_block_workspace,
work1,
work2,
work_h,
split_v_h_storage,
split_work_h_storage,
active_cols,
cutlass_workspace,
active_problem_sizes,
active_ptr_a,
active_ptr_b,
active_ptr_c,
active_ptr_d,
active_lda,
active_ldb,
active_ldc,
active_ldd,
batch,
k,
block_end,
cols);
} else if (!use_lowp_block) {
apply_trailing_update_cpp(trailing, v_block, t_block_workspace, work1, work2);
} else {
auto work_h = view_workspace3(work_h_storage, batch, superpanel, cols);
apply_512_lowp_update_cpp(
h,
trailing,
v_block_h,
v_block,
t_block_workspace,
work1,
work2,
work_h,
split_v_h_storage,
split_work_h_storage,
cutlass_workspace,
batch,
k,
block_end,
cols);
}
}
finalize_zero_tail_active_cols_512_kernel<<<batch, THREADS>>>(
h.data_ptr<float>(),
tau.data_ptr<float>(),
active_cols.data_ptr<int>(),
batch);
check_cuda(cudaGetLastError(), "finalize_zero_tail_active_cols_512");
}
void qr_1024_superpanel32_driver(torch::Tensor h,
torch::Tensor tau,
torch::Tensor v_panel_storage,
torch::Tensor v_block_storage,
torch::Tensor v_block_h_storage,
torch::Tensor t_panel_workspace,
torch::Tensor t_block_workspace,
torch::Tensor local_work1_storage,
torch::Tensor local_work2_storage,
torch::Tensor work1_storage,
torch::Tensor work2_storage,
torch::Tensor work_h_storage,
torch::Tensor cutlass_workspace) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "qr_1024_superpanel32_driver expects CUDA tensors");
TORCH_CHECK(v_panel_storage.is_cuda() && v_block_storage.is_cuda() && v_block_h_storage.is_cuda(), "V workspaces must be CUDA");
TORCH_CHECK(t_panel_workspace.is_cuda() && t_block_workspace.is_cuda(), "T workspaces must be CUDA");
TORCH_CHECK(local_work1_storage.is_cuda() && local_work2_storage.is_cuda(), "local workspaces must be CUDA");
TORCH_CHECK(work1_storage.is_cuda() && work2_storage.is_cuda() && work_h_storage.is_cuda(), "update workspaces must be CUDA");
TORCH_CHECK(cutlass_workspace.is_cuda(), "cutlass workspace must be CUDA");
TORCH_CHECK(h.scalar_type() == torch::kFloat32 && tau.scalar_type() == torch::kFloat32, "h/tau must be float32");
TORCH_CHECK(v_panel_storage.scalar_type() == torch::kFloat32 && v_block_storage.scalar_type() == torch::kFloat32, "V workspaces must be float32");
TORCH_CHECK(v_block_h_storage.scalar_type() == torch::kFloat16, "v_block_h_storage must be float16");
TORCH_CHECK(t_panel_workspace.scalar_type() == torch::kFloat32 && t_block_workspace.scalar_type() == torch::kFloat32, "T workspaces must be float32");
TORCH_CHECK(local_work1_storage.scalar_type() == torch::kFloat32 && local_work2_storage.scalar_type() == torch::kFloat32, "local workspaces must be float32");
TORCH_CHECK(work1_storage.scalar_type() == torch::kFloat32 && work2_storage.scalar_type() == torch::kFloat32, "update workspaces must be float32");
TORCH_CHECK(work_h_storage.scalar_type() == torch::kFloat16, "work_h_storage must be float16");
TORCH_CHECK(cutlass_workspace.scalar_type() == torch::kUInt8, "cutlass workspace must be uint8");
TORCH_CHECK(h.is_contiguous() && tau.is_contiguous(), "h/tau must be contiguous");
TORCH_CHECK(v_panel_storage.is_contiguous() && v_block_storage.is_contiguous() && v_block_h_storage.is_contiguous(), "V workspaces must be contiguous");
TORCH_CHECK(t_panel_workspace.is_contiguous() && t_block_workspace.is_contiguous(), "T workspaces must be contiguous");
TORCH_CHECK(local_work1_storage.is_contiguous() && local_work2_storage.is_contiguous(), "local workspaces must be contiguous");
TORCH_CHECK(work1_storage.is_contiguous() && work2_storage.is_contiguous() && work_h_storage.is_contiguous(), "update workspaces must be contiguous");
TORCH_CHECK(cutlass_workspace.is_contiguous(), "cutlass workspace must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 1024 && h.size(2) == 1024, "h must be batch x 1024 x 1024");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 1024, "tau must be batch x 1024");
TORCH_CHECK(t_panel_workspace.dim() == 4 && t_panel_workspace.size(0) >= 4 && t_panel_workspace.size(2) == 8 && t_panel_workspace.size(3) == 8, "t panel workspace has wrong shape");
TORCH_CHECK(t_block_workspace.dim() == 3 && t_block_workspace.size(1) == 32 && t_block_workspace.size(2) == 32, "t block workspace has wrong shape");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(tau.size(0) == batch && t_panel_workspace.size(1) == batch && t_block_workspace.size(0) == batch, "batch mismatch");
if (batch == 0) {
return;
}
constexpr int panel = 8;
constexpr int superpanel = 32;
constexpr int lowp_min_trailing_cols = 512;
for (int k = 0; k < 1024; k += superpanel) {
const int block_end = k + superpanel;
const bool has_trailing = block_end < 1024;
for (int kk = k; kk < block_end; kk += panel) {
const int next_col = kk + panel;
auto v = view_workspace3(v_panel_storage, batch, 1024 - kk, panel);
auto t = t_panel_workspace.select(0, (kk - k) / panel);
geqrf_1024_panel_smem(h, tau, kk, panel);
if (next_col < block_end || has_trailing) {
pack_v_panel(h, v, kk, panel);
make_t_panel(v, tau.narrow(1, kk, panel), t, panel);
}
if (next_col < block_end) {
auto local_trailing = h.narrow(1, kk, 1024 - kk).narrow(2, next_col, block_end - next_col);
auto local_work1 = view_workspace3(local_work1_storage, batch, panel, block_end - next_col);
auto local_work2 = view_workspace3(local_work2_storage, batch, panel, block_end - next_col);
apply_trailing_update_cpp(local_trailing, v, t, local_work1, local_work2);
}
}
if (!has_trailing) {
continue;
}
auto v_block = view_workspace3(v_block_storage, batch, 1024 - k, superpanel);
auto v_block_h = view_workspace3(v_block_h_storage, batch, 1024 - k, superpanel);
auto trailing = h.narrow(1, k, 1024 - k).narrow(2, block_end, 1024 - block_end);
const int cols = 1024 - block_end;
const bool use_lowp_block = cols >= lowp_min_trailing_cols;
if (use_lowp_block) {
pack_v_panel_half(h, v_block, v_block_h, k, superpanel);
} else {
pack_v_panel(h, v_block, k, superpanel);
}
merge_p8_tree_32(v_block, t_panel_workspace, t_block_workspace);
auto work1 = view_workspace3(work1_storage, batch, superpanel, cols);
auto work2 = view_workspace3(work2_storage, batch, superpanel, cols);
if (use_lowp_block) {
at::bmm_out(work1, v_block.transpose(1, 2), trailing);
at::bmm_out(work2, t_block_workspace.transpose(1, 2), work1);
auto work_h = view_workspace3(work_h_storage, batch, superpanel, cols);
work_h.copy_(work2);
update_1024_w32_cutlass(h, v_block_h, work_h, cutlass_workspace, k, block_end);
} else {
apply_trailing_update_cpp(trailing, v_block, t_block_workspace, work1, work2);
}
}
}
void qr_4096_superpanel32_driver(torch::Tensor h,
torch::Tensor tau,
torch::Tensor v_panel_storage,
torch::Tensor v_block_storage,
torch::Tensor t_panel_workspace,
torch::Tensor t_block_workspace,
torch::Tensor local_work1_storage,
torch::Tensor local_work2_storage,
torch::Tensor work1_storage,
torch::Tensor work2_storage) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "qr_4096_superpanel32_driver expects CUDA tensors");
TORCH_CHECK(v_panel_storage.is_cuda() && v_block_storage.is_cuda(), "V workspaces must be CUDA");
TORCH_CHECK(t_panel_workspace.is_cuda() && t_block_workspace.is_cuda(), "T workspaces must be CUDA");
TORCH_CHECK(local_work1_storage.is_cuda() && local_work2_storage.is_cuda(), "local workspaces must be CUDA");
TORCH_CHECK(work1_storage.is_cuda() && work2_storage.is_cuda(), "update workspaces must be CUDA");
TORCH_CHECK(h.scalar_type() == torch::kFloat32 && tau.scalar_type() == torch::kFloat32, "h/tau must be float32");
TORCH_CHECK(v_panel_storage.scalar_type() == torch::kFloat32 && v_block_storage.scalar_type() == torch::kFloat32, "V workspaces must be float32");
TORCH_CHECK(t_panel_workspace.scalar_type() == torch::kFloat32 && t_block_workspace.scalar_type() == torch::kFloat32, "T workspaces must be float32");
TORCH_CHECK(local_work1_storage.scalar_type() == torch::kFloat32 && local_work2_storage.scalar_type() == torch::kFloat32, "local workspaces must be float32");
TORCH_CHECK(work1_storage.scalar_type() == torch::kFloat32 && work2_storage.scalar_type() == torch::kFloat32, "update workspaces must be float32");
TORCH_CHECK(h.is_contiguous() && tau.is_contiguous(), "h/tau must be contiguous");
TORCH_CHECK(v_panel_storage.is_contiguous() && v_block_storage.is_contiguous(), "V workspaces must be contiguous");
TORCH_CHECK(t_panel_workspace.is_contiguous() && t_block_workspace.is_contiguous(), "T workspaces must be contiguous");
TORCH_CHECK(local_work1_storage.is_contiguous() && local_work2_storage.is_contiguous(), "local workspaces must be contiguous");
TORCH_CHECK(work1_storage.is_contiguous() && work2_storage.is_contiguous(), "update workspaces must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 4096 && h.size(2) == 4096, "h must be batch x 4096 x 4096");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 4096, "tau must be batch x 4096");
TORCH_CHECK(t_panel_workspace.dim() == 4 && t_panel_workspace.size(0) >= 4 && t_panel_workspace.size(2) == 8 && t_panel_workspace.size(3) == 8, "t panel workspace has wrong shape");
TORCH_CHECK(t_block_workspace.dim() == 3 && t_block_workspace.size(1) == 32 && t_block_workspace.size(2) == 32, "t block workspace has wrong shape");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(tau.size(0) == batch && t_panel_workspace.size(1) == batch && t_block_workspace.size(0) == batch, "batch mismatch");
if (batch == 0) {
return;
}
constexpr int panel = 8;
constexpr int superpanel = 32;
for (int k = 0; k < 4096; k += superpanel) {
const int block_end = k + superpanel;
const bool has_trailing = block_end < 4096;
for (int kk = k; kk < block_end; kk += panel) {
const int next_col = kk + panel;
auto v = view_workspace3(v_panel_storage, batch, 4096 - kk, panel);
auto t = t_panel_workspace.select(0, (kk - k) / panel);
if (next_col < block_end || has_trailing) {
geqrf_4096_panel_smem_pack(h, tau, kk, panel, v, t);
} else {
geqrf_4096_panel_smem(h, tau, kk, panel);
}
if (next_col < block_end) {
auto local_trailing = h.narrow(1, kk, 4096 - kk).narrow(2, next_col, block_end - next_col);
auto local_work1 = view_workspace3(local_work1_storage, batch, panel, block_end - next_col);
auto local_work2 = view_workspace3(local_work2_storage, batch, panel, block_end - next_col);
apply_trailing_update_cpp(local_trailing, v, t, local_work1, local_work2);
}
}
if (!has_trailing) {
continue;
}
auto v_block = view_workspace3(v_block_storage, batch, 4096 - k, superpanel);
pack_v_panel(h, v_block, k, superpanel);
merge_p8_tree_32(v_block, t_panel_workspace, t_block_workspace);
auto trailing = h.narrow(1, k, 4096 - k).narrow(2, block_end, 4096 - block_end);
const int cols = 4096 - block_end;
auto work1 = view_workspace3(work1_storage, batch, superpanel, cols);
auto work2 = view_workspace3(work2_storage, batch, superpanel, cols);
apply_trailing_update_cpp(trailing, v_block, t_block_workspace, work1, work2);
}
}
void qr_2048_superpanel64_cutlass_driver(torch::Tensor h,
torch::Tensor tau,
torch::Tensor v_panel_storage,
torch::Tensor v_block_storage,
torch::Tensor v_block_h_storage,
torch::Tensor t_panel_workspace,
torch::Tensor t_block_workspace,
torch::Tensor local_work1_storage,
torch::Tensor local_work2_storage,
torch::Tensor work1_storage,
torch::Tensor work2_storage,
torch::Tensor work_h_storage,
torch::Tensor cutlass_workspace) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "qr_2048_superpanel64_cutlass_driver expects CUDA tensors");
TORCH_CHECK(v_panel_storage.is_cuda() && v_block_storage.is_cuda() && v_block_h_storage.is_cuda(), "V workspaces must be CUDA");
TORCH_CHECK(t_panel_workspace.is_cuda() && t_block_workspace.is_cuda(), "T workspaces must be CUDA");
TORCH_CHECK(local_work1_storage.is_cuda() && local_work2_storage.is_cuda(), "local workspaces must be CUDA");
TORCH_CHECK(work1_storage.is_cuda() && work2_storage.is_cuda() && work_h_storage.is_cuda(), "update workspaces must be CUDA");
TORCH_CHECK(cutlass_workspace.is_cuda(), "cutlass workspace must be CUDA");
TORCH_CHECK(h.scalar_type() == torch::kFloat32 && tau.scalar_type() == torch::kFloat32, "h/tau must be float32");
TORCH_CHECK(v_panel_storage.scalar_type() == torch::kFloat32 && v_block_storage.scalar_type() == torch::kFloat32, "V workspaces must be float32");
TORCH_CHECK(v_block_h_storage.scalar_type() == torch::kFloat16, "half V workspace must be float16");
TORCH_CHECK(t_panel_workspace.scalar_type() == torch::kFloat32 && t_block_workspace.scalar_type() == torch::kFloat32, "T workspaces must be float32");
TORCH_CHECK(local_work1_storage.scalar_type() == torch::kFloat32 && local_work2_storage.scalar_type() == torch::kFloat32, "local workspaces must be float32");
TORCH_CHECK(work1_storage.scalar_type() == torch::kFloat32 && work2_storage.scalar_type() == torch::kFloat32, "update workspaces must be float32");
TORCH_CHECK(work_h_storage.scalar_type() == torch::kFloat16, "half work workspace must be float16");
TORCH_CHECK(cutlass_workspace.scalar_type() == torch::kUInt8, "cutlass workspace must be uint8");
TORCH_CHECK(h.is_contiguous() && tau.is_contiguous(), "h/tau must be contiguous");
TORCH_CHECK(v_panel_storage.is_contiguous() && v_block_storage.is_contiguous() && v_block_h_storage.is_contiguous(), "V workspaces must be contiguous");
TORCH_CHECK(t_panel_workspace.is_contiguous() && t_block_workspace.is_contiguous(), "T workspaces must be contiguous");
TORCH_CHECK(local_work1_storage.is_contiguous() && local_work2_storage.is_contiguous(), "local workspaces must be contiguous");
TORCH_CHECK(work1_storage.is_contiguous() && work2_storage.is_contiguous() && work_h_storage.is_contiguous(), "update workspaces must be contiguous");
TORCH_CHECK(cutlass_workspace.is_contiguous(), "cutlass workspace must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 2048 && h.size(2) == 2048, "h must be batch x 2048 x 2048");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 2048, "tau must be batch x 2048");
TORCH_CHECK(t_panel_workspace.dim() == 4 && t_panel_workspace.size(0) >= 8 && t_panel_workspace.size(2) == 8 && t_panel_workspace.size(3) == 8, "t panel workspace has wrong shape");
TORCH_CHECK(t_block_workspace.dim() == 3 && t_block_workspace.size(1) == 64 && t_block_workspace.size(2) == 64, "t block workspace has wrong shape");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(tau.size(0) == batch && t_panel_workspace.size(1) == batch && t_block_workspace.size(0) == batch, "batch mismatch");
if (batch == 0) {
return;
}
constexpr int N = 2048;
constexpr int panel = 8;
constexpr int superpanel = 64;
for (int k = 0; k < N; k += superpanel) {
const int block_end = k + superpanel;
const bool has_trailing = block_end < N;
for (int kk = k; kk < block_end; kk += panel) {
const int next_col = kk + panel;
auto v = view_workspace3(v_panel_storage, batch, N - kk, panel);
auto t = t_panel_workspace.select(0, (kk - k) / panel);
if (next_col < block_end || has_trailing) {
geqrf_2048_panel_smem_pack(h, tau, kk, panel, v, t);
} else {
geqrf_2048_panel_smem(h, tau, kk, panel);
}
if (next_col < block_end) {
auto local_trailing = h.narrow(1, kk, N - kk).narrow(2, next_col, block_end - next_col);
auto local_work1 = view_workspace3(local_work1_storage, batch, panel, block_end - next_col);
auto local_work2 = view_workspace3(local_work2_storage, batch, panel, block_end - next_col);
apply_trailing_update_cpp(local_trailing, v, t, local_work1, local_work2);
}
}
if (!has_trailing) {
continue;
}
auto v_block = view_workspace3(v_block_storage, batch, N - k, superpanel);
auto v_block_h = view_workspace3(v_block_h_storage, batch, N - k, superpanel);
pack_v_panel_half(h, v_block, v_block_h, k, superpanel);
make_t_panel(v_block, tau.narrow(1, k, superpanel), t_block_workspace, superpanel);
auto trailing = h.narrow(1, k, N - k).narrow(2, block_end, N - block_end);
const int cols = N - block_end;
auto work1 = view_workspace3(work1_storage, batch, superpanel, cols);
auto work2 = view_workspace3(work2_storage, batch, superpanel, cols);
auto work_h = view_workspace3(work_h_storage, batch, superpanel, cols);
at::bmm_out(work1, v_block.transpose(1, 2), trailing);
at::bmm_out(work2, t_block_workspace.transpose(1, 2), work1);
work_h.copy_(work2);
update_2048_w64_cutlass(h, v_block_h, work_h, cutlass_workspace, k, block_end);
}
}
void qr_4096_superpanel64_cutlass_driver(torch::Tensor h,
torch::Tensor tau,
torch::Tensor v_panel_storage,
torch::Tensor v_block_storage,
torch::Tensor v_block_h_storage,
torch::Tensor t_panel_workspace,
torch::Tensor t_block_workspace,
torch::Tensor local_work1_storage,
torch::Tensor local_work2_storage,
torch::Tensor work1_storage,
torch::Tensor work2_storage,
torch::Tensor work_h_storage,
torch::Tensor cutlass_workspace) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "qr_4096_superpanel64_cutlass_driver expects CUDA tensors");
TORCH_CHECK(v_panel_storage.is_cuda() && v_block_storage.is_cuda() && v_block_h_storage.is_cuda(), "V workspaces must be CUDA");
TORCH_CHECK(t_panel_workspace.is_cuda() && t_block_workspace.is_cuda(), "T workspaces must be CUDA");
TORCH_CHECK(local_work1_storage.is_cuda() && local_work2_storage.is_cuda(), "local workspaces must be CUDA");
TORCH_CHECK(work1_storage.is_cuda() && work2_storage.is_cuda() && work_h_storage.is_cuda(), "update workspaces must be CUDA");
TORCH_CHECK(cutlass_workspace.is_cuda(), "cutlass workspace must be CUDA");
TORCH_CHECK(h.scalar_type() == torch::kFloat32 && tau.scalar_type() == torch::kFloat32, "h/tau must be float32");
TORCH_CHECK(v_panel_storage.scalar_type() == torch::kFloat32 && v_block_storage.scalar_type() == torch::kFloat32, "V workspaces must be float32");
TORCH_CHECK(v_block_h_storage.scalar_type() == torch::kFloat16, "half V workspace must be float16");
TORCH_CHECK(t_panel_workspace.scalar_type() == torch::kFloat32 && t_block_workspace.scalar_type() == torch::kFloat32, "T workspaces must be float32");
TORCH_CHECK(local_work1_storage.scalar_type() == torch::kFloat32 && local_work2_storage.scalar_type() == torch::kFloat32, "local workspaces must be float32");
TORCH_CHECK(work1_storage.scalar_type() == torch::kFloat32 && work2_storage.scalar_type() == torch::kFloat32, "update workspaces must be float32");
TORCH_CHECK(work_h_storage.scalar_type() == torch::kFloat16, "half work workspace must be float16");
TORCH_CHECK(cutlass_workspace.scalar_type() == torch::kUInt8, "cutlass workspace must be uint8");
TORCH_CHECK(h.is_contiguous() && tau.is_contiguous(), "h/tau must be contiguous");
TORCH_CHECK(v_panel_storage.is_contiguous() && v_block_storage.is_contiguous() && v_block_h_storage.is_contiguous(), "V workspaces must be contiguous");
TORCH_CHECK(t_panel_workspace.is_contiguous() && t_block_workspace.is_contiguous(), "T workspaces must be contiguous");
TORCH_CHECK(local_work1_storage.is_contiguous() && local_work2_storage.is_contiguous(), "local workspaces must be contiguous");
TORCH_CHECK(work1_storage.is_contiguous() && work2_storage.is_contiguous() && work_h_storage.is_contiguous(), "update workspaces must be contiguous");
TORCH_CHECK(cutlass_workspace.is_contiguous(), "cutlass workspace must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 4096 && h.size(2) == 4096, "h must be batch x 4096 x 4096");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 4096, "tau must be batch x 4096");
TORCH_CHECK(t_panel_workspace.dim() == 4 && t_panel_workspace.size(0) >= 8 && t_panel_workspace.size(2) == 8 && t_panel_workspace.size(3) == 8, "t panel workspace has wrong shape");
TORCH_CHECK(t_block_workspace.dim() == 3 && t_block_workspace.size(1) == 64 && t_block_workspace.size(2) == 64, "t block workspace has wrong shape");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(tau.size(0) == batch && t_panel_workspace.size(1) == batch && t_block_workspace.size(0) == batch, "batch mismatch");
if (batch == 0) {
return;
}
constexpr int panel = 8;
constexpr int superpanel = 64;
for (int k = 0; k < 4096; k += superpanel) {
const int block_end = k + superpanel;
const bool has_trailing = block_end < 4096;
for (int kk = k; kk < block_end; kk += panel) {
const int next_col = kk + panel;
auto v = view_workspace3(v_panel_storage, batch, 4096 - kk, panel);
auto t = t_panel_workspace.select(0, (kk - k) / panel);
if (next_col < block_end || has_trailing) {
geqrf_4096_panel_smem_pack(h, tau, kk, panel, v, t);
} else {
geqrf_4096_panel_smem(h, tau, kk, panel);
}
if (next_col < block_end) {
auto local_trailing = h.narrow(1, kk, 4096 - kk).narrow(2, next_col, block_end - next_col);
auto local_work1 = view_workspace3(local_work1_storage, batch, panel, block_end - next_col);
auto local_work2 = view_workspace3(local_work2_storage, batch, panel, block_end - next_col);
apply_trailing_update_cpp(local_trailing, v, t, local_work1, local_work2);
}
}
if (!has_trailing) {
continue;
}
auto v_block = view_workspace3(v_block_storage, batch, 4096 - k, superpanel);
auto v_block_h = view_workspace3(v_block_h_storage, batch, 4096 - k, superpanel);
pack_v_panel_half(h, v_block, v_block_h, k, superpanel);
make_t_panel(v_block, tau.narrow(1, k, superpanel), t_block_workspace, superpanel);
auto trailing = h.narrow(1, k, 4096 - k).narrow(2, block_end, 4096 - block_end);
const int cols = 4096 - block_end;
auto work1 = view_workspace3(work1_storage, batch, superpanel, cols);
auto work2 = view_workspace3(work2_storage, batch, superpanel, cols);
auto work_h = view_workspace3(work_h_storage, batch, superpanel, cols);
at::bmm_out(work1, v_block.transpose(1, 2), trailing);
at::bmm_out(work2, t_block_workspace.transpose(1, 2), work1);
work_h.copy_(work2);
update_4096_w64_cutlass(h, v_block_h, work_h, cutlass_workspace, k, block_end);
}
}
void qr_4096_panel64_driver(torch::Tensor h,
torch::Tensor tau,
torch::Tensor v_storage,
torch::Tensor t_workspace,
torch::Tensor work1_storage,
torch::Tensor work2_storage) {
TORCH_CHECK(h.is_cuda() && tau.is_cuda(), "qr_4096_panel64_driver expects CUDA tensors");
TORCH_CHECK(v_storage.is_cuda() && t_workspace.is_cuda() && work1_storage.is_cuda() && work2_storage.is_cuda(), "workspaces must be CUDA");
TORCH_CHECK(h.scalar_type() == torch::kFloat32 && tau.scalar_type() == torch::kFloat32, "h/tau must be float32");
TORCH_CHECK(v_storage.scalar_type() == torch::kFloat32 && t_workspace.scalar_type() == torch::kFloat32, "V/T workspaces must be float32");
TORCH_CHECK(work1_storage.scalar_type() == torch::kFloat32 && work2_storage.scalar_type() == torch::kFloat32, "update workspaces must be float32");
TORCH_CHECK(h.is_contiguous() && tau.is_contiguous(), "h/tau must be contiguous");
TORCH_CHECK(v_storage.is_contiguous() && t_workspace.is_contiguous() && work1_storage.is_contiguous() && work2_storage.is_contiguous(), "workspaces must be contiguous");
TORCH_CHECK(h.dim() == 3 && h.size(1) == 4096 && h.size(2) == 4096, "h must be batch x 4096 x 4096");
TORCH_CHECK(tau.dim() == 2 && tau.size(1) == 4096, "tau must be batch x 4096");
TORCH_CHECK(t_workspace.dim() == 3 && t_workspace.size(1) == 64 && t_workspace.size(2) == 64, "t workspace must be batch x 64 x 64");
const int batch = static_cast<int>(h.size(0));
TORCH_CHECK(tau.size(0) == batch && t_workspace.size(0) == batch, "batch mismatch");
if (batch == 0) {
return;
}
constexpr int panel = 64;
for (int k = 0; k < 4096; k += panel) {
const int next_col = k + panel;
geqrf_4096_panel(h, tau, k, panel);
if (next_col >= 4096) {
continue;
}
auto v = view_workspace3(v_storage, batch, 4096 - k, panel);
pack_v_panel(h, v, k, panel);
make_t_panel(v, tau.narrow(1, k, panel), t_workspace, panel);
auto trailing = h.narrow(1, k, 4096 - k).narrow(2, next_col, 4096 - next_col);
const int cols = 4096 - next_col;
auto work1 = view_workspace3(work1_storage, batch, panel, cols);
auto work2 = view_workspace3(work2_storage, batch, panel, cols);
apply_trailing_update_cpp(trailing, v, t_workspace, work1, work2);
}
}
"""
if torch.cuda.is_available():
_native_module = load_inline(
name="qrv2_1024lp_v2",
cpp_sources=[CPP_SRC],
cuda_sources=[CUDA_SRC],
functions=[
"geqrf_32_panel",
"geqrf_32_warp",
"geqrf_32_warp_out",
"geqrf_32_warp_make",
"geqrf_176_panel",
"geqrf_176_panel_smem_t",
"geqrf_176_panel_smem_pack_t",
"geqrf_352_panel",
"geqrf_352_panel_smem_t",
"geqrf_512_panel",
"geqrf_512_panel_smem",
"geqrf_512_panel_smem_pack",
"geqrf_512_panel_smem_pack_h",
"geqrf_1024_panel",
"geqrf_1024_panel_smem",
"geqrf_2048_panel",
"geqrf_2048_panel_smem",
"geqrf_2048_panel_smem_pack",
"geqrf_4096_panel",
"geqrf_4096_panel_smem",
"geqrf_4096_panel_smem_pack",
"geqrf_176_panel_t",
"geqrf_352_panel_t",
"geqrf_512_panel_t",
"geqrf_1024_panel_t",
"geqrf_2048_panel_t",
"pack_v_panel",
"pack_v_panel_half",
"make_t_panel",
"merge_p8_tree_32",
"qr_176_panel8_driver",
"qr_512_superpanel32_active_driver",
"qr_1024_superpanel32_driver",
"qr_4096_panel64_driver",
"qr_4096_superpanel32_driver",
"qr_4096_superpanel64_cutlass_driver",
"detect_zero_tail_rank_512",
"detect_clustered_effective_cols_512",
"detect_nearrank_duplicate_rank_1024",
"finalize_nearrank_tail_1024",
"update_512_w16_fused",
"update_512_w16_hacc",
"update_512_w16_cutlass",
"update_512_w32_cutlass",
"update_1024_w16_hacc",
"update_1024_w32_cutlass",
"update_4096_w64_cutlass",
"update_2048_w4",
"update_2048_w4_tile8",
"update_2048_w8_tile8",
],
extra_cflags=["-O3"],
extra_cuda_cflags=[
"-O3",
"--ptxas-options=-O3",
"--use_fast_math",
"-DCUTLASS_ENABLE_TENSOR_CORE_MMA=1",
"-gencode=arch=compute_100a,code=sm_100a",
"-I/usr/local/cutlass/include",
"-I/opt/cutlass/include",
"-I/workspace/cutlass/include",
"-I/cutlass/include",
],
verbose=False,
)
else:
_native_module = None
def _make_v_inplace(panel_h: torch.Tensor, width: int) -> torch.Tensor:
v = panel_h[:, :, :width]
v.tril_(-1)
diag = torch.arange(width, device=panel_h.device)
v[:, diag, diag] = 1.0
return v
def _make_t(
v: torch.Tensor,
tau: torch.Tensor,
width: int,
use_native_t: bool,
) -> torch.Tensor:
batch = v.shape[0]
if use_native_t and width <= 128 and v.is_cuda and _native_module is not None:
t = torch.empty((batch, width, width), device=v.device, dtype=v.dtype)
_native_module.make_t_panel(v, tau, t, width)
return t
t = torch.zeros((batch, width, width), device=v.device, dtype=v.dtype)
for j in range(width):
tau_j = tau[:, j]
if j > 0:
col = -tau_j[:, None] * torch.bmm(
v[:, j:, :j].transpose(1, 2),
v[:, j:, j : j + 1],
).squeeze(-1)
t[:, :j, j] = torch.bmm(t[:, :j, :j], col.unsqueeze(-1)).squeeze(-1)
t[:, j, j] = tau_j
return t
def _workspace_view_3d(storage: torch.Tensor, batch: int, rows: int, width: int) -> torch.Tensor:
return storage[: batch * rows * width].view(batch, rows, width)
def _panel_for_n(n: int) -> int:
if n == 32:
return _PANEL_32
if n == 2048:
return _PANEL_2048
if n == 4096:
return _PANEL_4096
if n == 352:
return _PANEL_352
return _PANEL
def _apply_trailing_update(
trailing: torch.Tensor,
v: torch.Tensor,
t: torch.Tensor,
precompute_u: bool,
) -> None:
work = torch.bmm(v.transpose(1, 2), trailing)
if precompute_u:
u = torch.bmm(v, t.transpose(1, 2))
torch.baddbmm(trailing, u, work, beta=1.0, alpha=-1.0, out=trailing)
else:
work = torch.bmm(t.transpose(1, 2), work)
torch.baddbmm(trailing, v, work, beta=1.0, alpha=-1.0, out=trailing)
def _apply_trailing_update_lowp(
trailing: torch.Tensor,
v_half: torch.Tensor,
v: torch.Tensor,
t: torch.Tensor,
h: torch.Tensor,
k: int,
next_col: int,
work1: torch.Tensor,
work2: torch.Tensor,
work_h: torch.Tensor,
cutlass_workspace: torch.Tensor,
v_half_16: torch.Tensor | None = None,
work_h_16: torch.Tensor | None = None,
) -> None:
torch.bmm(v.transpose(1, 2), trailing, out=work1)
torch.bmm(t.transpose(1, 2), work1, out=work2)
work_h.copy_(work2)
n = h.shape[-1]
width = v_half.shape[-1]
if n == 512 and width == 16:
_native_module.update_512_w16_cutlass(h, v_half, work_h, cutlass_workspace, k, next_col)
elif n == 512 and width == 32:
_native_module.update_512_w32_cutlass(h, v_half, work_h, cutlass_workspace, k, next_col)
elif n == 512 and width in (64, 128):
if v_half_16 is None or work_h_16 is None:
raise RuntimeError("missing 512 split low precision workspace")
for offset in range(0, width, 16):
v_half_16.copy_(v_half[:, :, offset : offset + 16])
work_h_16.copy_(work_h[:, offset : offset + 16, :])
_native_module.update_512_w16_cutlass(h, v_half_16, work_h_16, cutlass_workspace, k, next_col)
else:
raise RuntimeError("unsupported low precision update shape")
def _native_geqrf_panel(
h: torch.Tensor,
tau: torch.Tensor,
n: int,
k: int,
width: int,
t: torch.Tensor | None = None,
) -> None:
if n == 32:
_native_module.geqrf_32_panel(h, tau, k, width)
elif n == 176:
if t is not None and width == 8:
_native_module.geqrf_176_panel_smem_t(h, tau, t, k, width)
elif t is not None:
_native_module.geqrf_176_panel_t(h, tau, t, k, width)
else:
_native_module.geqrf_176_panel(h, tau, k, width)
elif n == 352:
if t is not None and width == 8:
_native_module.geqrf_352_panel_smem_t(h, tau, t, k, width)
elif t is not None:
_native_module.geqrf_352_panel_t(h, tau, t, k, width)
else:
_native_module.geqrf_352_panel(h, tau, k, width)
elif n == 512:
if _USE_SMEM_PANEL_512 and t is None and width == 8:
_native_module.geqrf_512_panel_smem(h, tau, k, width)
elif t is not None:
_native_module.geqrf_512_panel_t(h, tau, t, k, width)
else:
_native_module.geqrf_512_panel(h, tau, k, width)
elif n == 1024:
if _USE_SMEM_PANEL_1024 and t is None and width == 8:
_native_module.geqrf_1024_panel_smem(h, tau, k, width)
elif t is not None:
_native_module.geqrf_1024_panel_t(h, tau, t, k, width)
else:
_native_module.geqrf_1024_panel(h, tau, k, width)
elif n == 2048:
if _USE_SMEM_PANEL_2048 and t is None and (width == 4 or width == 8):
_native_module.geqrf_2048_panel_smem(h, tau, k, width)
elif t is not None:
_native_module.geqrf_2048_panel_t(h, tau, t, k, width)
else:
_native_module.geqrf_2048_panel(h, tau, k, width)
elif n == 4096:
_native_module.geqrf_4096_panel(h, tau, k, width)
def _blocked_qr_superpanel_512(data: torch.Tensor) -> output_t:
h = data.clone()
batch, n, _ = h.shape
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
panel = _PANEL
superpanel = _SUPERPANEL_512
precompute_u = n in _USE_PRECOMPUTE_U_NS
use_lowp_update = n in _USE_LOW_PRECISION_UPDATE_NS
v_panel_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
v_block_workspace = torch.empty((batch * n * superpanel,), device=h.device, dtype=h.dtype)
v_block_h_workspace = (
torch.empty((batch * n * superpanel,), device=h.device, dtype=torch.float16)
if use_lowp_update
else None
)
lowp_work1_workspace = (
torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
if use_lowp_update
else None
)
lowp_work2_workspace = (
torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
if use_lowp_update
else None
)
lowp_work_h_workspace = (
torch.empty((batch * superpanel * n,), device=h.device, dtype=torch.float16)
if use_lowp_update
else None
)
split_v_h_workspace = (
torch.empty((batch * n * 16,), device=h.device, dtype=torch.float16)
if use_lowp_update and superpanel > 16
else None
)
split_work_h_workspace = (
torch.empty((batch * 16 * n,), device=h.device, dtype=torch.float16)
if use_lowp_update and superpanel > 16
else None
)
cutlass_workspace = (
torch.empty((4 * 1024 * 1024,), device=h.device, dtype=torch.uint8)
if use_lowp_update
else None
)
t_panel_workspace = torch.empty((superpanel // panel, batch, panel, panel), device=h.device, dtype=h.dtype)
t_block_workspace = torch.empty((batch, superpanel, superpanel), device=h.device, dtype=h.dtype)
local_work1_workspace = torch.empty((batch * panel * superpanel,), device=h.device, dtype=h.dtype)
local_work2_workspace = torch.empty((batch * panel * superpanel,), device=h.device, dtype=h.dtype)
active_problem_sizes = torch.empty((batch, 3), device=h.device, dtype=torch.int32)
active_ptr_a = torch.empty((batch,), device=h.device, dtype=torch.int64)
active_ptr_b = torch.empty((batch,), device=h.device, dtype=torch.int64)
active_ptr_c = torch.empty((batch,), device=h.device, dtype=torch.int64)
active_ptr_d = torch.empty((batch,), device=h.device, dtype=torch.int64)
active_lda = torch.empty((batch,), device=h.device, dtype=torch.int64)
active_ldb = torch.empty((batch,), device=h.device, dtype=torch.int64)
active_ldc = torch.empty((batch,), device=h.device, dtype=torch.int64)
active_ldd = torch.empty((batch,), device=h.device, dtype=torch.int64)
_native_module.qr_512_superpanel32_active_driver(
h,
tau,
v_panel_workspace,
v_block_workspace,
v_block_h_workspace,
t_panel_workspace,
t_block_workspace,
local_work1_workspace,
local_work2_workspace,
lowp_work1_workspace,
lowp_work2_workspace,
lowp_work_h_workspace,
split_v_h_workspace,
split_work_h_workspace,
cutlass_workspace,
active_problem_sizes,
active_ptr_a,
active_ptr_b,
active_ptr_c,
active_ptr_d,
active_lda,
active_ldb,
active_ldc,
active_ldd,
)
return h, tau
for k in range(0, n, superpanel):
block_width = min(superpanel, n - k)
block_end = k + block_width
merge_panel_ts = []
use_merged_t = panel == 8 and block_width in (16, 32, 64, 128) and block_end < n
use_lowp_block = use_lowp_update and (n - block_end) >= _LOWP_MIN_TRAILING_COLS_512
v_block = None
v_block_h = None
if use_merged_t:
v_block = _workspace_view_3d(v_block_workspace, batch, n - k, block_width)
if use_lowp_block:
v_block_h = _workspace_view_3d(v_block_h_workspace, batch, n - k, block_width)
for kk in range(k, block_end, panel):
width = min(panel, block_end - kk)
next_col = kk + width
if use_merged_t:
v = _workspace_view_3d(v_panel_workspace, batch, n - kk, width)
t = t_panel_workspace[(kk - k) // panel]
if v_block_h is not None:
_native_module.geqrf_512_panel_smem_pack_h(h, tau, kk, width, v, v_block, v_block_h, t, k, kk - k)
else:
_native_module.geqrf_512_panel_smem_pack(h, tau, kk, width, v, v_block, t, k, kk - k)
else:
_native_geqrf_panel(h, tau, n, kk, width)
v = None
t = None
needs_local_update = next_col < block_end
if not needs_local_update and not use_merged_t:
continue
if v is None:
v = _workspace_view_3d(v_panel_workspace, batch, n - kk, width)
_native_module.pack_v_panel(h, v, kk, width)
if t is None:
panel_tau = tau[:, kk : kk + width]
t = _make_t(v, panel_tau, width, True)
if use_merged_t:
merge_panel_ts.append(t)
if needs_local_update:
local_trailing = h[:, kk:, next_col:block_end]
_apply_trailing_update(local_trailing, v, t, precompute_u)
if block_end >= n:
continue
if v_block is None:
v_block = _workspace_view_3d(v_block_workspace, batch, n - k, block_width)
_native_module.pack_v_panel(h, v_block, k, block_width)
if use_merged_t and len(merge_panel_ts) == block_width // panel:
t_block = _merge_p8_t_tree_maybe_native(v_block, merge_panel_ts, t_panel_workspace)
else:
t_block = _make_t(v_block, tau[:, k:block_end], block_width, True)
trailing = h[:, k:, block_end:]
if use_lowp_block and v_block_h is not None:
cols = n - block_end
work1 = _workspace_view_3d(lowp_work1_workspace, batch, block_width, cols)
work2 = _workspace_view_3d(lowp_work2_workspace, batch, block_width, cols)
work_h = _workspace_view_3d(lowp_work_h_workspace, batch, block_width, cols)
_apply_trailing_update_lowp(
trailing,
v_block_h,
v_block,
t_block,
h,
k,
block_end,
work1,
work2,
work_h,
cutlass_workspace,
_workspace_view_3d(split_v_h_workspace, batch, n - k, 16)
if split_v_h_workspace is not None
else None,
_workspace_view_3d(split_work_h_workspace, batch, 16, cols)
if split_work_h_workspace is not None
else None,
)
elif _USE_FUSED_512_FP32_UPDATE and block_width == 16 and _native_module is not None:
_native_module.update_512_w16_fused(h, v_block, t_block, k, block_end)
else:
_apply_trailing_update(trailing, v_block, t_block, precompute_u)
return h, tau
def _align_up(value: int, multiple: int) -> int:
return ((value + multiple - 1) // multiple) * multiple
def _detect_homogeneous_zero_tail_rank(data: torch.Tensor) -> int | None:
rank = int(_native_module.detect_zero_tail_rank_512(data))
if rank < 0:
return None
return rank
def _detect_clustered_effective_cols_512(data: torch.Tensor) -> int | None:
cols = int(_native_module.detect_clustered_effective_cols_512(data, 1.0e-6))
if cols < 0:
return None
return cols
def _blocked_qr_superpanel_512_effective(data: torch.Tensor, true_cols: int) -> output_t:
h = data.clone()
batch, n, _ = h.shape
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
panel = _PANEL
superpanel = _SUPERPANEL_512
precompute_u = n in _USE_PRECOMPUTE_U_NS
active_cols = min(n, _align_up(true_cols, panel))
v_panel_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
v_block_workspace = torch.empty((batch * n * superpanel,), device=h.device, dtype=h.dtype)
t_panel_workspace = torch.empty((superpanel // panel, batch, panel, panel), device=h.device, dtype=h.dtype)
for k in range(0, active_cols, superpanel):
block_width = min(superpanel, active_cols - k)
block_end = k + block_width
merge_panel_ts = []
use_merged_t = panel == 8 and block_width in (16, 32, 64, 128) and block_end < active_cols
v_block = None
if use_merged_t:
v_block = _workspace_view_3d(v_block_workspace, batch, n - k, block_width)
for kk in range(k, block_end, panel):
width = min(panel, block_end - kk)
next_col = kk + width
if use_merged_t:
v = _workspace_view_3d(v_panel_workspace, batch, n - kk, width)
t = t_panel_workspace[(kk - k) // panel]
_native_module.geqrf_512_panel_smem_pack(h, tau, kk, width, v, v_block, t, k, kk - k)
else:
_native_geqrf_panel(h, tau, n, kk, width)
v = None
t = None
needs_local_update = next_col < block_end
if not needs_local_update and not use_merged_t:
continue
if v is None:
v = _workspace_view_3d(v_panel_workspace, batch, n - kk, width)
_native_module.pack_v_panel(h, v, kk, width)
if t is None:
panel_tau = tau[:, kk : kk + width]
t = _make_t(v, panel_tau, width, True)
if use_merged_t:
merge_panel_ts.append(t)
if needs_local_update:
local_trailing = h[:, kk:, next_col:block_end]
_apply_trailing_update(local_trailing, v, t, precompute_u)
if block_end >= active_cols:
continue
if v_block is None:
v_block = _workspace_view_3d(v_block_workspace, batch, n - k, block_width)
_native_module.pack_v_panel(h, v_block, k, block_width)
if use_merged_t and len(merge_panel_ts) == block_width // panel:
t_block = _merge_p8_t_tree_maybe_native(v_block, merge_panel_ts, t_panel_workspace)
else:
t_block = _make_t(v_block, tau[:, k:block_end], block_width, True)
trailing = h[:, k:, block_end:active_cols]
_apply_trailing_update(trailing, v_block, t_block, precompute_u)
tau[:, true_cols:].zero_()
h[:, :, true_cols:].zero_()
return h, tau
def _blocked_qr_32_warp(data: torch.Tensor) -> output_t:
return _native_module.geqrf_32_warp_make(data)
def _blocked_qr_176_driver(data: torch.Tensor) -> output_t:
h = data.clone()
batch, n, _ = h.shape
panel = 8
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
v_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
t_workspace = torch.empty((batch, panel, panel), device=h.device, dtype=h.dtype)
work1_workspace = torch.empty((batch * panel * n,), device=h.device, dtype=h.dtype)
work2_workspace = torch.empty((batch * panel * n,), device=h.device, dtype=h.dtype)
_native_module.qr_176_panel8_driver(
h,
tau,
v_workspace,
t_workspace,
work1_workspace,
work2_workspace,
)
return h, tau
def _merge_two_panel_t(v_block: torch.Tensor, t1: torch.Tensor, t2: torch.Tensor) -> torch.Tensor:
batch = v_block.shape[0]
width = t1.shape[1]
merged_width = width * 2
t = torch.zeros((batch, merged_width, merged_width), device=v_block.device, dtype=v_block.dtype)
t[:, :width, :width] = t1
t[:, width:, width:] = t2
cross = torch.bmm(v_block[:, :, :width].transpose(1, 2), v_block[:, :, width:merged_width])
t[:, :width, width:] = -torch.bmm(torch.bmm(t1, cross), t2)
return t
def _merge_two_p8_t(v_block: torch.Tensor, t1: torch.Tensor, t2: torch.Tensor) -> torch.Tensor:
return _merge_two_panel_t(v_block, t1, t2)
def _merge_p8_t_tree(v_block: torch.Tensor, panel_ts: list[torch.Tensor]) -> torch.Tensor:
if len(panel_ts) == 2:
return _merge_two_p8_t(v_block, panel_ts[0], panel_ts[1])
if len(panel_ts) > 2 and len(panel_ts) % 2 == 0:
half = len(panel_ts) // 2
split = 8 * half
left = _merge_p8_t_tree(v_block[:, :, :split], panel_ts[:half])
right = _merge_p8_t_tree(v_block[:, :, split : 2 * split], panel_ts[half:])
return _merge_two_panel_t(v_block, left, right)
raise RuntimeError("unsupported p8 merge tree width")
def _merge_p8_t_tree_maybe_native(
v_block: torch.Tensor,
panel_ts: list[torch.Tensor],
t_panel_workspace: torch.Tensor | None,
) -> torch.Tensor:
if (
_native_module is not None
and t_panel_workspace is not None
and v_block.is_cuda
and v_block.shape[2] == 32
and len(panel_ts) == 4
):
t = torch.empty((v_block.shape[0], 32, 32), device=v_block.device, dtype=v_block.dtype)
_native_module.merge_p8_tree_32(v_block, t_panel_workspace[:4], t)
return t
return _merge_p8_t_tree(v_block, panel_ts)
def _blocked_qr_superpanel_generic(data: torch.Tensor, superpanel: int) -> output_t:
h = data.clone()
batch, n, _ = h.shape
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
panel = _panel_for_n(n)
precompute_u = n in _USE_PRECOMPUTE_U_NS
use_lowp_update = n == 1024 and n in _USE_LOW_PRECISION_UPDATE_NS and superpanel == 16
v_panel_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
v_block_workspace = torch.empty((batch * n * superpanel,), device=h.device, dtype=h.dtype)
v_block_h_workspace = (
torch.empty((batch * n * superpanel,), device=h.device, dtype=torch.float16)
if use_lowp_update
else None
)
lowp_work1_workspace = (
torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
if use_lowp_update
else None
)
lowp_work2_workspace = (
torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
if use_lowp_update
else None
)
lowp_work_h_workspace = (
torch.empty((batch * superpanel * n,), device=h.device, dtype=torch.float16)
if use_lowp_update
else None
)
t_panel_workspace = torch.empty((max(1, superpanel // panel), batch, panel, panel), device=h.device, dtype=h.dtype)
for k in range(0, n, superpanel):
block_width = min(superpanel, n - k)
block_end = k + block_width
merge_panel_ts = []
use_merged_t = panel == 8 and block_width in (16, 32, 64, 128) and block_end < n
use_lowp_block = (
use_lowp_update
and block_width == 16
and (n - block_end) >= _LOWP_MIN_TRAILING_COLS_1024
)
for kk in range(k, block_end, panel):
width = min(panel, block_end - kk)
next_col = kk + width
_native_geqrf_panel(h, tau, n, kk, width)
needs_local_update = next_col < block_end
if not needs_local_update and not use_merged_t:
continue
v = _workspace_view_3d(v_panel_workspace, batch, n - kk, width)
_native_module.pack_v_panel(h, v, kk, width)
if use_merged_t and block_width == 32 and width == panel:
t = t_panel_workspace[(kk - k) // panel]
_native_module.make_t_panel(v, tau[:, kk : kk + width], t, width)
else:
t = _make_t(v, tau[:, kk : kk + width], width, True)
if use_merged_t:
merge_panel_ts.append(t)
if needs_local_update:
local_trailing = h[:, kk:, next_col:block_end]
_apply_trailing_update(local_trailing, v, t, precompute_u)
if block_end >= n:
continue
v_block = _workspace_view_3d(v_block_workspace, batch, n - k, block_width)
_native_module.pack_v_panel(h, v_block, k, block_width)
if use_merged_t and len(merge_panel_ts) == block_width // panel:
t_block = _merge_p8_t_tree_maybe_native(v_block, merge_panel_ts, t_panel_workspace)
else:
t_block = _make_t(v_block, tau[:, k:block_end], block_width, True)
trailing = h[:, k:, block_end:]
if use_lowp_block:
cols = n - block_end
v_block_h = _workspace_view_3d(v_block_h_workspace, batch, n - k, block_width)
_native_module.pack_v_panel_half(h, v_block, v_block_h, k, block_width)
work1 = _workspace_view_3d(lowp_work1_workspace, batch, block_width, cols)
work2 = _workspace_view_3d(lowp_work2_workspace, batch, block_width, cols)
work_h = _workspace_view_3d(lowp_work_h_workspace, batch, block_width, cols)
_apply_trailing_update_lowp(
trailing,
v_block_h,
v_block,
t_block,
h,
k,
block_end,
work1,
work2,
work_h,
None,
)
else:
_apply_trailing_update(trailing, v_block, t_block, precompute_u)
return h, tau
def _blocked_qr_1024_driver(data: torch.Tensor) -> output_t:
h = data.clone()
batch, n, _ = h.shape
panel = 8
superpanel = 32
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
v_panel_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
v_block_workspace = torch.empty((batch * n * superpanel,), device=h.device, dtype=h.dtype)
v_block_h_workspace = torch.empty((batch * n * superpanel,), device=h.device, dtype=torch.float16)
t_panel_workspace = torch.empty((superpanel // panel, batch, panel, panel), device=h.device, dtype=h.dtype)
t_block_workspace = torch.empty((batch, superpanel, superpanel), device=h.device, dtype=h.dtype)
local_work1_workspace = torch.empty((batch * panel * superpanel,), device=h.device, dtype=h.dtype)
local_work2_workspace = torch.empty((batch * panel * superpanel,), device=h.device, dtype=h.dtype)
work1_workspace = torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
work2_workspace = torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
work_h_workspace = torch.empty((batch * superpanel * n,), device=h.device, dtype=torch.float16)
cutlass_workspace = torch.empty((16 * 1024 * 1024,), device=h.device, dtype=torch.uint8)
_native_module.qr_1024_superpanel32_driver(
h,
tau,
v_panel_workspace,
v_block_workspace,
v_block_h_workspace,
t_panel_workspace,
t_block_workspace,
local_work1_workspace,
local_work2_workspace,
work1_workspace,
work2_workspace,
work_h_workspace,
cutlass_workspace,
)
return h, tau
def _blocked_qr_4096_driver(data: torch.Tensor) -> output_t:
h = data.clone()
batch, n, _ = h.shape
panel = _PANEL_4096
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
v_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
t_workspace = torch.empty((batch, panel, panel), device=h.device, dtype=h.dtype)
work1_workspace = torch.empty((batch * panel * n,), device=h.device, dtype=h.dtype)
work2_workspace = torch.empty((batch * panel * n,), device=h.device, dtype=h.dtype)
_native_module.qr_4096_panel64_driver(
h,
tau,
v_workspace,
t_workspace,
work1_workspace,
work2_workspace,
)
return h, tau
def _blocked_qr_4096_superpanel_driver(data: torch.Tensor) -> output_t:
h = data.clone()
batch, n, _ = h.shape
panel = 8
superpanel = _SUPERPANEL_4096
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
v_panel_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
v_block_workspace = torch.empty((batch * n * superpanel,), device=h.device, dtype=h.dtype)
t_panel_workspace = torch.empty((superpanel // panel, batch, panel, panel), device=h.device, dtype=h.dtype)
t_block_workspace = torch.empty((batch, superpanel, superpanel), device=h.device, dtype=h.dtype)
local_work1_workspace = torch.empty((batch * panel * superpanel,), device=h.device, dtype=h.dtype)
local_work2_workspace = torch.empty((batch * panel * superpanel,), device=h.device, dtype=h.dtype)
work1_workspace = torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
work2_workspace = torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
_native_module.qr_4096_superpanel32_driver(
h,
tau,
v_panel_workspace,
v_block_workspace,
t_panel_workspace,
t_block_workspace,
local_work1_workspace,
local_work2_workspace,
work1_workspace,
work2_workspace,
)
return h, tau
def _blocked_qr_4096_cutlass64_driver(data: torch.Tensor) -> output_t:
h = data.clone()
batch, n, _ = h.shape
panel = 8
superpanel = 64
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
v_panel_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
v_block_workspace = torch.empty((batch * n * superpanel,), device=h.device, dtype=h.dtype)
v_block_h_workspace = torch.empty((batch * n * superpanel,), device=h.device, dtype=torch.float16)
t_panel_workspace = torch.empty((superpanel // panel, batch, panel, panel), device=h.device, dtype=h.dtype)
t_block_workspace = torch.empty((batch, superpanel, superpanel), device=h.device, dtype=h.dtype)
local_work1_workspace = torch.empty((batch * panel * superpanel,), device=h.device, dtype=h.dtype)
local_work2_workspace = torch.empty((batch * panel * superpanel,), device=h.device, dtype=h.dtype)
work1_workspace = torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
work2_workspace = torch.empty((batch * superpanel * n,), device=h.device, dtype=h.dtype)
work_h_workspace = torch.empty((batch * superpanel * n,), device=h.device, dtype=torch.float16)
cutlass_workspace = torch.empty((32 * 1024 * 1024,), device=h.device, dtype=torch.uint8)
_native_module.qr_4096_superpanel64_cutlass_driver(
h,
tau,
v_panel_workspace,
v_block_workspace,
v_block_h_workspace,
t_panel_workspace,
t_block_workspace,
local_work1_workspace,
local_work2_workspace,
work1_workspace,
work2_workspace,
work_h_workspace,
cutlass_workspace,
)
return h, tau
def _detect_nearrank_duplicate_tail_1024(data: torch.Tensor) -> int | None:
rank = int(_native_module.detect_nearrank_duplicate_rank_1024(data, 1.0e-3))
if rank < 0:
return None
return rank
def _blocked_qr_superpanel_generic_effective_nearrank(
data: torch.Tensor,
superpanel: int,
true_cols: int,
) -> output_t:
h = data.clone()
batch, n, _ = h.shape
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
panel = _panel_for_n(n)
precompute_u = n in _USE_PRECOMPUTE_U_NS
active_cols = true_cols
v_panel_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
v_block_workspace = torch.empty((batch * n * superpanel,), device=h.device, dtype=h.dtype)
t_panel_workspace = torch.empty((max(1, superpanel // panel), batch, panel, panel), device=h.device, dtype=h.dtype)
for k in range(0, active_cols, superpanel):
block_width = min(superpanel, active_cols - k)
block_end = k + block_width
merge_panel_ts = []
use_merged_t = panel == 8 and block_width in (16, 32, 64, 128) and block_end < active_cols
for kk in range(k, block_end, panel):
width = min(panel, block_end - kk)
next_col = kk + width
_native_geqrf_panel(h, tau, n, kk, width)
needs_local_update = next_col < block_end
if not needs_local_update and not use_merged_t:
continue
v = _workspace_view_3d(v_panel_workspace, batch, n - kk, width)
_native_module.pack_v_panel(h, v, kk, width)
if use_merged_t and block_width == 32 and width == panel:
t = t_panel_workspace[(kk - k) // panel]
_native_module.make_t_panel(v, tau[:, kk : kk + width], t, width)
else:
t = _make_t(v, tau[:, kk : kk + width], width, True)
if use_merged_t:
merge_panel_ts.append(t)
if needs_local_update:
local_trailing = h[:, kk:, next_col:block_end]
_apply_trailing_update(local_trailing, v, t, precompute_u)
if block_end >= active_cols:
continue
v_block = _workspace_view_3d(v_block_workspace, batch, n - k, block_width)
_native_module.pack_v_panel(h, v_block, k, block_width)
if use_merged_t and len(merge_panel_ts) == block_width // panel:
t_block = _merge_p8_t_tree_maybe_native(v_block, merge_panel_ts, t_panel_workspace)
else:
t_block = _make_t(v_block, tau[:, k:block_end], block_width, True)
trailing = h[:, k:, block_end:active_cols]
_apply_trailing_update(trailing, v_block, t_block, precompute_u)
_native_module.finalize_nearrank_tail_1024(h, tau, true_cols)
return h, tau
def _blocked_qr_2048_native_update(data: torch.Tensor) -> output_t:
h = data.clone()
batch, n, _ = h.shape
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
panel = 4
v_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
t_workspace = torch.empty((batch, panel, panel), device=h.device, dtype=h.dtype)
for k in range(0, n, panel):
width = min(panel, n - k)
next_col = k + width
if next_col >= n:
_native_geqrf_panel(h, tau, n, k, width)
continue
v = _workspace_view_3d(v_workspace, batch, n - k, width)
t = t_workspace
_native_module.geqrf_2048_panel_smem_pack(h, tau, k, width, v, t)
_native_module.update_2048_w4(h, v, t, k, next_col)
return h, tau
def _blocked_qr_2048_pack_blas_update(data: torch.Tensor) -> output_t:
h = data.clone()
batch, n, _ = h.shape
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
panel = _PANEL_2048
precompute_u = n in _USE_PRECOMPUTE_U_NS
v_workspace = torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
t_workspace = torch.empty((batch, panel, panel), device=h.device, dtype=h.dtype)
for k in range(0, n, panel):
width = min(panel, n - k)
next_col = k + width
if next_col >= n:
_native_geqrf_panel(h, tau, n, k, width)
continue
v = _workspace_view_3d(v_workspace, batch, n - k, width)
t = t_workspace
_native_module.geqrf_2048_panel_smem_pack(h, tau, k, width, v, t)
trailing = h[:, k:, next_col:]
_apply_trailing_update(trailing, v, t, precompute_u)
return h, tau
def _blocked_qr(data: torch.Tensor, panel: int) -> output_t:
h = data.clone()
batch, n, _ = h.shape
tau = torch.empty((batch, n), device=h.device, dtype=h.dtype)
panel = _panel_for_n(n)
use_native_panel = n in _NATIVE_PANEL_NS and _native_module is not None
use_native_t = use_native_panel
precompute_u = n in _USE_PRECOMPUTE_U_NS
v_workspace = (
torch.empty((batch * n * panel,), device=h.device, dtype=h.dtype)
if use_native_panel
else None
)
t_workspace = (
torch.empty((batch, panel, panel), device=h.device, dtype=h.dtype)
if use_native_panel
else None
)
for k in range(0, n, panel):
width = min(panel, n - k)
next_col = k + width
has_trailing = next_col < n
use_panel_t = use_native_panel and n in _PANEL_T_NS and has_trailing
t = None
if use_native_panel:
if use_panel_t:
t = t_workspace
_native_geqrf_panel(h, tau, n, k, width, t)
panel_tau = tau[:, k : k + width]
panel_h = None
else:
panel_h, panel_tau = torch.geqrf(h[:, k:, k : k + width].contiguous())
h[:, k:, k : k + width] = panel_h
tau[:, k : k + width] = panel_tau
if not has_trailing:
continue
if use_native_panel:
v = _workspace_view_3d(v_workspace, batch, n - k, width)
_native_module.pack_v_panel(h, v, k, width)
if t is None:
t = _make_t(v, panel_tau, width, use_native_t)
if _USE_NATIVE_UPDATE_2048 and n == 2048 and width == 4 and _native_module is not None:
_native_module.update_2048_w4_tile8(h, v, t, k, next_col)
continue
else:
v = _make_v_inplace(panel_h, width)
t = _make_t(v, panel_tau, width, use_native_t)
trailing = h[:, k:, next_col:]
_apply_trailing_update(trailing, v, t, precompute_u)
return h, tau
def custom_kernel(data: input_t) -> output_t:
if (
data.is_cuda
and data.dtype == torch.float32
and data.dim() == 3
and data.shape[-1] in _BLOCKED_NS
):
if data.shape[-1] == 32 and _native_module is not None:
return _blocked_qr_32_warp(
data.contiguous() if not data.is_contiguous() else data,
)
n = data.shape[-1]
if n == 176 and _native_module is not None:
return _blocked_qr_176_driver(
data.contiguous() if not data.is_contiguous() else data,
)
if n == 512 and n in _SUPERPANEL_NS and _native_module is not None:
data_in = data.contiguous() if not data.is_contiguous() else data
rank = _detect_homogeneous_zero_tail_rank(data_in)
if rank is not None:
return _blocked_qr_superpanel_512_effective(data_in, rank)
return _blocked_qr_superpanel_512(data_in)
if n == 1024 and n in _SUPERPANEL_NS and _native_module is not None:
data_in = data.contiguous() if not data.is_contiguous() else data
nearrank_cols = _detect_nearrank_duplicate_tail_1024(data_in)
if nearrank_cols is not None:
return _blocked_qr_superpanel_generic_effective_nearrank(
data_in,
_SUPERPANEL_1024,
nearrank_cols,
)
if _USE_NATIVE_1024_SUPERPANEL_DRIVER and _SUPERPANEL_1024 == 32:
return _blocked_qr_1024_driver(data_in)
return _blocked_qr_superpanel_generic(data_in, _SUPERPANEL_1024)
if n == 2048 and n in _SUPERPANEL_NS and _native_module is not None:
if _USE_2048_PACK_BLAS_UPDATE:
return _blocked_qr_2048_pack_blas_update(
data.contiguous() if not data.is_contiguous() else data,
)
return _blocked_qr_superpanel_generic(
data.contiguous() if not data.is_contiguous() else data,
_SUPERPANEL_2048,
)
if n == 4096 and _USE_NATIVE_4096_CUTLASS64_DRIVER and _PANEL_4096 == 8 and _SUPERPANEL_4096 == 64 and _native_module is not None:
return _blocked_qr_4096_cutlass64_driver(
data.contiguous() if not data.is_contiguous() else data,
)
if n == 4096 and _USE_NATIVE_4096_TILE_DRIVER and _PANEL_4096 == 8 and _SUPERPANEL_4096 == 32 and _native_module is not None:
return _blocked_qr_4096_superpanel_driver(
data.contiguous() if not data.is_contiguous() else data,
)
if n == 4096 and _USE_NATIVE_4096_DRIVER and _PANEL_4096 == 64 and _native_module is not None:
return _blocked_qr_4096_driver(
data.contiguous() if not data.is_contiguous() else data,
)
return _blocked_qr(
data.contiguous() if not data.is_contiguous() else data,
_panel_for_n(n),
)
return torch.geqrf(data)
scrolls · 5220 lines total
Source code from GPU Mode and the KernelBot dataset · June 9 Researcher Reciprocity License v1.0
Best evidence level for this revision: reported
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