submission 843146
Frosty40 · python · License unknown
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submission.py
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Compatibility
measured onNVIDIA B200
declared hardwareNVIDIA B200
architecturessm_100
dtypesfp32
Benchmark evidence
1 measurement across 1 GPU, fastest first.
Operation / workload
Hardware
Latency
Rank
Observed
Reported · How evidence levels are derived →
Source and license
sourceavailable
revision digestsha256:8d048f950ddd20809be688cf4dbc884dab0b764e2548d3b6a171070b2690e1d4
license declaredunknown
license concludedunknown
authorsFrosty40
imported2026-08-26
Techniques
Extracted from the mirrored source by pattern, never inferred. Each row cites its line.
mma
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;shared-memory
extern __shared__ float smem[];split-k
__global__ void gram128_wmma3x_splitk_kernel(const float* __restrict__ X,Kernel source
submission.py2175 lines
import torch
from torch.utils.cpp_extension import load_inline
from task import input_t, output_t
# CUDA kernels inlined for self-contained submission
_CUDA = r"""/* Fully-fused QR kernels: panel_factor + m2_trailing + small_qr
* All with ceiling division fixes and bounds checking */
#include <torch/extension.h>
#include <cuda_runtime.h>
#include <cublas_v2.h>
#include <ATen/cuda/CUDAContext.h>
#include <mma.h>
using namespace nvcuda;
#define M16 16
#define N16 16
#define K8 8
#define FNB 32
#define FTW 16
__device__ __forceinline__ float blockReduceSum(float val, float* scratch) {
int lane = threadIdx.x & 31, wid = threadIdx.x >> 5;
#pragma unroll
for (int o = 16; o > 0; o >>= 1) val += __shfl_down_sync(0xffffffff, val, o);
if (lane == 0) scratch[wid] = val;
__syncthreads();
int nwarp = (blockDim.x + 31) >> 5;
val = (threadIdx.x < nwarp) ? scratch[lane] : 0.0f;
if (wid == 0) { for (int o = 16; o > 0; o >>= 1) val += __shfl_down_sync(0xffffffff, val, o); }
if (threadIdx.x == 0) scratch[0] = val;
__syncthreads();
return scratch[0];
}
__global__ void small_qr_kernel(float* __restrict__ A, float* __restrict__ tau, int B, int n) {
int b = blockIdx.x; if (b >= B) return;
float* Ab = A + (long)b * n * n; float* tb = tau + (long)b * n;
extern __shared__ float smem[];
int tid = threadIdx.x, nt = blockDim.x, lane = tid & 31;
for (int k = 0; k < n - 1; k += FNB) {
int jb = (FNB < n - k) ? FNB : (n - k);
int m = n - k;
float* sp = smem;
float* scr = sp + m * jb;
float* w = scr + 32;
float* sc = w + FNB;
float* ct = sc + 3;
for (int idx = tid; idx < m * jb; idx += nt) { int r = idx / jb, c = idx % jb; sp[idx] = Ab[(long)(k + r) * n + (k + c)]; }
__syncthreads();
for (int jj = 0; jj < jb; ++jj) {
float loc = 0.0f;
for (int r = jj + 1 + tid; r < m; r += nt) { float v = sp[r * jb + jj]; loc += v * v; }
float xt2 = blockReduceSum(loc, scr);
if (tid == 0) {
float x0 = sp[jj * jb + jj], beta, tv, inv;
if (xt2 <= 1.17549435e-38f) { beta = x0; tv = 0.0f; inv = 0.0f; }
else { float nr = sqrtf(x0 * x0 + xt2); beta = (x0 >= 0.0f) ? -nr : nr; tv = (beta - x0) / beta; inv = 1.0f / (x0 - beta); }
sc[0] = beta; sc[1] = tv; sc[2] = inv; sp[jj * jb + jj] = beta; tb[k + jj] = tv;
}
__syncthreads();
float tv = sc[1], inv = sc[2];
for (int r = jj + 1 + tid; r < m; r += nt) sp[r * jb + jj] *= inv;
__syncthreads();
if (jj + 1 < jb && tv != 0.0f) {
for (int c = jj + 1 + tid; c < jb; c += nt) w[c] = 0.0f; __syncthreads();
float wl[FNB];
#pragma unroll
for (int c = 0; c < FNB; ++c) wl[c] = 0.0f;
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : sp[r * jb + jj]; const float* row = &sp[r * jb + jj + 1];
#pragma unroll
for (int c = 0; c < FNB; ++c) if (jj + 1 + c < jb) wl[c] += vr * row[c];
}
#pragma unroll
for (int c = 0; c < FNB; ++c) { if (jj + 1 + c >= jb) break; float val = wl[c];
for (int o = 16; o > 0; o >>= 1) val += __shfl_down_sync(0xffffffff, val, o);
if (lane == 0) atomicAdd(&w[jj + 1 + c], val); }
__syncthreads();
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : sp[r * jb + jj]; float s = tv * vr; float* row = &sp[r * jb + jj + 1];
#pragma unroll
for (int c = 0; c < FNB; ++c) if (jj + 1 + c < jb) row[c] -= s * w[jj + 1 + c];
}
__syncthreads();
}
}
for (int idx = tid; idx < m * jb; idx += nt) { int r = idx / jb, c = idx % jb; Ab[(long)(k + r) * n + (k + c)] = sp[idx]; }
__syncthreads();
for (int c0 = k + jb; c0 < n; c0 += FTW) {
int tw = (FTW < n - c0) ? FTW : (n - c0);
for (int idx = tid; idx < m * tw; idx += nt) { int r = idx / tw, c = idx % tw; ct[r * FTW + c] = Ab[(long)(k + r) * n + (c0 + c)]; }
__syncthreads();
for (int jj = 0; jj < jb; ++jj) {
float tvj = tb[k + jj];
if (tvj == 0.0f) continue;
for (int c = tid; c < tw; c += nt) w[c] = 0.0f; __syncthreads();
float wl[FTW];
#pragma unroll
for (int c = 0; c < FTW; ++c) wl[c] = 0.0f;
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : sp[r * jb + jj]; const float* row = &ct[r * FTW];
#pragma unroll
for (int c = 0; c < FTW; ++c) if (c < tw) wl[c] += vr * row[c];
}
#pragma unroll
for (int c = 0; c < FTW; ++c) { if (c >= tw) break; float val = wl[c];
for (int o = 16; o > 0; o >>= 1) val += __shfl_down_sync(0xffffffff, val, o);
if (lane == 0) atomicAdd(&w[c], val); }
__syncthreads();
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : sp[r * jb + jj]; float s = tvj * vr; float* row = &ct[r * FTW];
#pragma unroll
for (int c = 0; c < FTW; ++c) if (c < tw) row[c] -= s * w[c];
}
__syncthreads();
}
for (int idx = tid; idx < m * tw; idx += nt) { int r = idx / tw, c = idx % tw; Ab[(long)(k + r) * n + (c0 + c)] = ct[r * FTW + c]; }
__syncthreads();
}
}
}
// v254: shape-conditional panel. Two kernels with identical Householder math;
// the host dispatches by batch B. The root (block-sync) kernel wins on the
// high-batch n512 family (B=640, GPU saturated / throughput-bound, so trading a
// barrier for redundant per-thread reflector compute costs more than it saves);
// the v253 fewer-syncs kernel wins on low-batch large-n (n1024 B=60, n2048 B=8,
// under-occupied / latency-bound, so cutting critical-path syncs helps and the
// redundant compute is free on idle ALUs). Threshold B<=128 -> fewsync.
// --- root panel kernel (block barriers; best at high occupancy / high batch) ---
__global__ void panel_factor_kernel_root(float* __restrict__ A, float* __restrict__ tau,
int B, int n, int k, int jb, int ld) {
int b = blockIdx.x; if (b >= B) return;
int m = n - k;
float* Ab = A + (long)b * n * n; float* tb = tau + (long)b * n;
extern __shared__ float smem[];
float* sp = smem; float* scratch = sp + (long)m * ld; float* w = scratch + 32; float* sc = w + jb;
int tid = threadIdx.x, nt = blockDim.x;
for (int idx = tid; idx < m * jb; idx += nt) { int r = idx / jb, c = idx % jb; sp[r * ld + c] = Ab[(long)(k + r) * n + (k + c)]; }
__syncthreads();
for (int jj = 0; jj < jb; ++jj) {
float loc = 0.0f;
for (int r = jj + 1 + tid; r < m; r += nt) { float v = sp[r * ld + jj]; loc += v * v; }
float xtail2 = blockReduceSum(loc, scratch);
if (tid == 0) {
float x0 = sp[jj * ld + jj], beta, tauv, inv;
if (xtail2 <= 1.17549435e-38f) { beta = x0; tauv = 0.0f; inv = 0.0f; }
else { float nrm = sqrtf(x0 * x0 + xtail2); beta = (x0 >= 0.0f) ? -nrm : nrm; tauv = (beta - x0) / beta; inv = 1.0f / (x0 - beta); }
sc[0] = beta; sc[1] = tauv; sc[2] = inv; sp[jj * ld + jj] = beta; tb[k + jj] = tauv;
}
__syncthreads();
float tauv = sc[1], inv = sc[2];
for (int r = jj + 1 + tid; r < m; r += nt) sp[r * ld + jj] *= inv;
__syncthreads();
if (jj + 1 < jb && tauv != 0.0f) {
int lane = tid & 31;
for (int c = jj + 1 + tid; c < jb; c += nt) w[c] = 0.0f; __syncthreads();
float wl[32];
for (int c = 0; c < 32; ++c) wl[c] = 0.0f;
for (int r = jj + tid; r < m; r += nt) { float vr = (r == jj) ? 1.0f : sp[r * ld + jj]; const float* row = &sp[r * ld + jj + 1];
for (int c = 0; c < 32; ++c) if (jj + 1 + c < jb) wl[c] += vr * row[c]; }
for (int c = 0; c < 32; ++c) { if (jj + 1 + c >= jb) break; float val = wl[c];
for (int o = 16; o > 0; o >>= 1) val += __shfl_down_sync(0xffffffff, val, o);
if (lane == 0) atomicAdd(&w[jj + 1 + c], val); }
__syncthreads();
for (int r = jj + tid; r < m; r += nt) { float vr = (r == jj) ? 1.0f : sp[r * ld + jj]; float s = tauv * vr; float* row = &sp[r * ld + jj + 1];
for (int c = 0; c < 32; ++c) if (jj + 1 + c < jb) row[c] -= s * w[jj + 1 + c]; }
__syncthreads();
}
}
for (int idx = tid; idx < m * jb; idx += nt) { int r = idx / jb, c = idx % jb; Ab[(long)(k + r) * n + (k + c)] = sp[r * ld + c]; }
}
// --- v253 fewer-syncs panel kernel (best at low occupancy / low batch) ---
__global__ void panel_factor_kernel_fewsync(float* __restrict__ A, float* __restrict__ tau,
int B, int n, int k, int jb, int ld) {
int b = blockIdx.x; if (b >= B) return;
int m = n - k;
float* Ab = A + (long)b * n * n; float* tb = tau + (long)b * n;
extern __shared__ float smem[];
float* sp = smem;
float* scratch = sp + (long)m * ld;
float* wpart = scratch + 32;
int tid = threadIdx.x, nt = blockDim.x;
int lane = tid & 31, warp = tid >> 5, nw = (nt + 31) >> 5;
for (int idx = tid; idx < m * jb; idx += nt) { int r = idx / jb, c = idx % jb; sp[r * ld + c] = Ab[(long)(k + r) * n + (k + c)]; }
__syncthreads();
for (int jj = 0; jj < jb; ++jj) {
// Read the pivot BEFORE the reduction so blockReduceSum's internal barriers
// separate this read from the redundant beta write-back below. Without this,
// warp 0's `sp[jj*ld+jj]=beta` write can race ahead of another warp's pivot
// read (warps schedule independently), corrupting the reflector at high occupancy.
float x0 = sp[jj * ld + jj];
// --- column norm below the diagonal; blockReduceSum broadcasts to all threads ---
float loc = 0.0f;
for (int r = jj + 1 + tid; r < m; r += nt) { float v = sp[r * ld + jj]; loc += v * v; }
float xtail2 = blockReduceSum(loc, scratch);
// --- Householder computed redundantly in every thread (no broadcast sync) ---
float beta, tauv, inv;
if (xtail2 <= 1.17549435e-38f) { beta = x0; tauv = 0.0f; inv = 0.0f; }
else { float nrm = sqrtf(x0 * x0 + xtail2); beta = (x0 >= 0.0f) ? -nrm : nrm; tauv = (beta - x0) / beta; inv = 1.0f / (x0 - beta); }
if (tid == 0) { sp[jj * ld + jj] = beta; tb[k + jj] = tauv; }
if (jj + 1 < jb && tauv != 0.0f) {
int ncol = jb - jj - 1; // trailing panel columns (<=31)
// accumulate w = v^T * A[:, jj+1:], scaling v on the fly
float wl[32];
#pragma unroll
for (int c = 0; c < 32; ++c) wl[c] = 0.0f;
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : (sp[r * ld + jj] * inv);
const float* row = &sp[r * ld + jj + 1];
#pragma unroll
for (int c = 0; c < 32; ++c) if (c < ncol) wl[c] += vr * row[c];
}
// one partial w-vector per warp (warp-reduced, no atomics)
#pragma unroll
for (int c = 0; c < 32; ++c) {
if (c >= ncol) break;
float val = wl[c];
for (int o = 16; o > 0; o >>= 1) val += __shfl_down_sync(0xffffffff, val, o);
if (lane == 0) wpart[warp * 32 + c] = val;
}
__syncthreads();
// each thread folds the partials into w (times tauv) in registers (no sync)
float wreg[32];
#pragma unroll
for (int c = 0; c < 32; ++c) {
if (c >= ncol) break;
float a = 0.0f;
for (int p = 0; p < nw; ++p) a += wpart[p * 32 + c];
wreg[c] = tauv * a;
}
// apply A[:, jj+1:] -= v * (tauv * w) and write the scaled reflector back
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : (sp[r * ld + jj] * inv);
float* row = &sp[r * ld + jj + 1];
#pragma unroll
for (int c = 0; c < 32; ++c) if (c < ncol) row[c] -= vr * wreg[c];
if (r > jj) sp[r * ld + jj] = vr;
}
__syncthreads();
} else {
// last column or null reflector: finalize the scaled v
for (int r = jj + 1 + tid; r < m; r += nt) sp[r * ld + jj] *= inv;
__syncthreads();
}
}
for (int idx = tid; idx < m * jb; idx += nt) { int r = idx / jb, c = idx % jb; Ab[(long)(k + r) * n + (k + c)] = sp[r * ld + c]; }
}
__global__ void m2_larfb_kernel(const float* __restrict__ Vg,
const float* __restrict__ Tg, float* __restrict__ Cg,
int B, int m, int nb, int N) {
int bid = blockIdx.x; if (bid >= B) return;
extern __shared__ float smem[];
float* V = smem;
float* T = V + m * nb;
float* C = T + nb * nb;
float* W = C + m * N;
float* Y = W + nb * N;
int tid = threadIdx.x, nt = blockDim.x, warp = tid >> 5, nw = nt >> 5;
for (int i = tid; i < m * nb; i += nt) V[i] = Vg[bid * m * nb + i];
for (int i = tid; i < nb * nb; i += nt) T[i] = Tg[bid * nb * nb + i];
for (int i = tid; i < m * N; i += nt) C[i] = Cg[bid * m * N + i];
__syncthreads();
int nb_tiles_m = (nb + M16 - 1) / M16;
int N_tiles_m = (N + M16 - 1) / M16;
int N_tiles_n = (N + N16 - 1) / N16;
int m_tiles_m = (m + M16 - 1) / M16;
for (int t = warp; t < nb_tiles_m * N_tiles_n; t += nw) {
int mt = (t / N_tiles_n) * M16;
int nt0 = (t % N_tiles_n) * N16;
int mt_end = min(mt + M16, nb);
int nt0_end = min(nt0 + N16, N);
int mt_valid = mt_end > mt;
int nt0_valid = nt0_end > nt0;
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int k = 0; k < m; k += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::col_major> a;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> b;
if (mt_valid) wmma::load_matrix_sync(a, V + k * nb + mt, nb);
else for (int i = 0; i < a.num_elements; ++i) a.x[i] = 0.0f;
if (nt0_valid) wmma::load_matrix_sync(b, C + k * N + nt0, N);
else for (int i = 0; i < b.num_elements; ++i) b.x[i] = 0.0f;
for (int i = 0; i < a.num_elements; ++i) a.x[i] = wmma::__float_to_tf32(a.x[i]);
for (int i = 0; i < b.num_elements; ++i) b.x[i] = wmma::__float_to_tf32(b.x[i]);
wmma::mma_sync(acc, a, b, acc);
}
if (mt_valid && nt0_valid) wmma::store_matrix_sync(W + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < nb_tiles_m * N_tiles_m; t += nw) {
int mt = (t / N_tiles_m) * M16;
int nt0 = (t % N_tiles_m) * M16;
int mt_end = min(mt + M16, nb);
int nt0_end = min(nt0 + N16, N);
int mt_valid = mt_end > mt;
int nt0_valid = nt0_end > nt0;
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int k = 0; k < nb; k += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> a;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> b;
if (mt_valid && k < nb) wmma::load_matrix_sync(a, T + mt * nb + k, nb);
else for (int i = 0; i < a.num_elements; ++i) a.x[i] = 0.0f;
if (k < nb && nt0_valid) wmma::load_matrix_sync(b, W + k * N + nt0, N);
else for (int i = 0; i < b.num_elements; ++i) b.x[i] = 0.0f;
for (int i = 0; i < a.num_elements; ++i) a.x[i] = wmma::__float_to_tf32(a.x[i]);
for (int i = 0; i < b.num_elements; ++i) b.x[i] = wmma::__float_to_tf32(b.x[i]);
wmma::mma_sync(acc, a, b, acc);
}
if (mt_valid && nt0_valid) wmma::store_matrix_sync(Y + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < m_tiles_m * N_tiles_m; t += nw) {
int mt = (t / N_tiles_m) * M16;
int nt0 = (t % N_tiles_m) * M16;
int mt_end = min(mt + M16, m);
int nt0_end = min(nt0 + N16, N);
int mt_valid = mt_end > mt;
int nt0_valid = nt0_end > nt0;
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int k = 0; k < nb; k += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> a;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> b;
if (mt_valid && k < nb) wmma::load_matrix_sync(a, V + mt * nb + k, nb);
else for (int i = 0; i < a.num_elements; ++i) a.x[i] = 0.0f;
if (k < nb && nt0_valid) wmma::load_matrix_sync(b, Y + k * N + nt0, N);
else for (int i = 0; i < b.num_elements; ++i) b.x[i] = 0.0f;
for (int i = 0; i < a.num_elements; ++i) a.x[i] = wmma::__float_to_tf32(a.x[i]);
for (int i = 0; i < b.num_elements; ++i) b.x[i] = wmma::__float_to_tf32(b.x[i]);
wmma::mma_sync(acc, a, b, acc);
}
if (mt_valid && nt0_valid) {
wmma::fragment<wmma::accumulator, M16, N16, K8, float> cf;
wmma::load_matrix_sync(cf, C + mt * N + nt0, N, wmma::mem_row_major);
for (int i = 0; i < acc.num_elements; ++i) acc.x[i] = cf.x[i] - acc.x[i];
wmma::store_matrix_sync(Cg + bid * m * N + mt * N + nt0, acc, N, wmma::mem_row_major);
}
}
}
// v316: FUSED WY update. Applies (I - V T V^T) to C in ONE launch (one block/matrix),
// computing T internally. V (masked unit-lower-trap) + C read from A[koff:, koff:].
// The wmma GEMMs are NARROW-N (where cuBLAS is weak), so in-kernel TC should win here.
__global__ void wy_apply_kernel(float* __restrict__ A, const float* __restrict__ tau,
int B, int n, int koff, int sub, int N) {
int b = blockIdx.x; if (b >= B) return;
float* Ab = A + (long)b * n * n;
const float* tb = tau + (long)b * n + koff;
int mrows = n - koff;
extern __shared__ float sh[];
float* V = sh; // mrows*sub (masked V in smem)
float* G = V + (long)mrows * sub; // sub*sub (C stays in global)
float* Tm = G + sub * sub; // sub*sub
float* Wm = Tm + sub * sub; // sub*N
float* Ym = Wm + sub * N; // sub*N
float* Cbase = Ab + (long)koff * n + (koff + sub); // C origin in global, row stride n
int tid = threadIdx.x, nt = blockDim.x, warp = tid >> 5, nw = nt >> 5;
for (int idx = tid; idx < mrows * sub; idx += nt) { int r = idx / sub, c = idx % sub;
float v = Ab[(long)(koff + r) * n + (koff + c)]; V[idx] = (r > c) ? v : (r == c ? 1.0f : 0.0f); }
__syncthreads();
for (int idx = tid; idx < sub * sub; idx += nt) { int i = idx / sub, j = idx % sub;
if (i <= j) { float s = 0.0f; for (int r = 0; r < mrows; ++r) s += V[r * sub + i] * V[r * sub + j];
G[i * sub + j] = s; G[j * sub + i] = s; } }
__syncthreads();
for (int jc = tid; jc < sub; jc += nt) {
for (int i = 0; i < sub; ++i) Tm[i * sub + jc] = 0.0f;
float mjj = (tb[jc] != 0.0f) ? (1.0f / tb[jc]) : 1.0e30f;
Tm[jc * sub + jc] = 1.0f / mjj;
for (int i = jc + 1; i < sub; ++i) {
float s = 0.0f;
for (int kk = jc; kk < i; ++kk) {
float mik = (i == kk) ? mjj : G[i * sub + kk];
s += mik * Tm[kk * sub + jc];
}
float mii = (tb[i] != 0.0f) ? (1.0f / tb[i]) : 1.0e30f;
Tm[i * sub + jc] = -s / mii;
}
}
__syncthreads();
int sub_tiles = (sub + M16 - 1) / M16;
int N_tiles_n = (N + N16 - 1) / N16;
int m_tiles = (mrows + M16 - 1) / M16;
for (int t = warp; t < sub_tiles * N_tiles_n; t += nw) { // W = V^T C
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16;
int mv = (mt < sub), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc; wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < mrows; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::col_major> a;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bb;
if (mv) wmma::load_matrix_sync(a, V + kk * sub + mt, sub); else for (int i=0;i<a.num_elements;++i) a.x[i]=0.0f;
if (nv) wmma::load_matrix_sync(bb, Cbase + (long)kk * n + nt0, n); else for (int i=0;i<bb.num_elements;++i) bb.x[i]=0.0f;
for (int i=0;i<a.num_elements;++i) a.x[i]=wmma::__float_to_tf32(a.x[i]);
for (int i=0;i<bb.num_elements;++i) bb.x[i]=wmma::__float_to_tf32(bb.x[i]);
wmma::mma_sync(acc, a, bb, acc);
}
if (mv && nv) wmma::store_matrix_sync(Wm + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < sub_tiles * N_tiles_n; t += nw) { // Y = T W
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16;
int mv = (mt < sub), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc; wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < sub; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> a;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bb;
if (mv) wmma::load_matrix_sync(a, Tm + mt * sub + kk, sub); else for (int i=0;i<a.num_elements;++i) a.x[i]=0.0f;
if (nv) wmma::load_matrix_sync(bb, Wm + kk * N + nt0, N); else for (int i=0;i<bb.num_elements;++i) bb.x[i]=0.0f;
for (int i=0;i<a.num_elements;++i) a.x[i]=wmma::__float_to_tf32(a.x[i]);
for (int i=0;i<bb.num_elements;++i) bb.x[i]=wmma::__float_to_tf32(bb.x[i]);
wmma::mma_sync(acc, a, bb, acc);
}
if (mv && nv) wmma::store_matrix_sync(Ym + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < m_tiles * N_tiles_n; t += nw) { // C -= V Y, write to A
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16;
int mv = (mt < mrows), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc; wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < sub; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> a;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bb;
if (mv) wmma::load_matrix_sync(a, V + mt * sub + kk, sub); else for (int i=0;i<a.num_elements;++i) a.x[i]=0.0f;
if (nv) wmma::load_matrix_sync(bb, Ym + kk * N + nt0, N); else for (int i=0;i<bb.num_elements;++i) bb.x[i]=0.0f;
for (int i=0;i<a.num_elements;++i) a.x[i]=wmma::__float_to_tf32(a.x[i]);
for (int i=0;i<bb.num_elements;++i) bb.x[i]=wmma::__float_to_tf32(bb.x[i]);
wmma::mma_sync(acc, a, bb, acc);
}
if (mv && nv) {
wmma::fragment<wmma::accumulator, M16, N16, K8, float> cf;
wmma::load_matrix_sync(cf, Cbase + (long)mt * n + nt0, n, wmma::mem_row_major);
for (int i = 0; i < acc.num_elements; ++i) acc.x[i] = cf.x[i] - acc.x[i];
wmma::store_matrix_sync(Cbase + (long)mt * n + nt0, acc, n, wmma::mem_row_major);
}
}
}
void wy_apply(torch::Tensor A, torch::Tensor tau, int64_t koff, int64_t sub, int64_t N) {
int B = A.size(0), n = A.size(1); int mrows = n - (int)koff;
size_t smem = (size_t)((long)mrows * sub + 2 * sub * sub + 2 * sub * N) * sizeof(float); // C stays in global
cudaFuncSetAttribute(wy_apply_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
wy_apply_kernel<<<B, 256, smem>>>(A.data_ptr<float>(), tau.data_ptr<float>(), B, n, (int)koff, (int)sub, (int)N);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "wy_apply: ", cudaGetErrorString(e), " smem=", smem);
}
__global__ void panel64_fused_kernel(float* __restrict__ A, float* __restrict__ tau,
int B, int n, int k0) {
int b = blockIdx.x; if (b >= B) return;
float* Ab = A + (long)b * n * n;
float* tb = tau + (long)b * n;
extern __shared__ float smem[];
int tid = threadIdx.x, nt = blockDim.x;
int lane = tid & 31, warp = tid >> 5, nw = (nt + 31) >> 5;
const int sub = 16;
const int ld = 17;
for (int q = 0; q < 4; ++q) {
int koff = k0 + q * sub;
int m = n - koff;
{
float* sp = smem;
float* scratch = sp + (long)m * ld;
float* wpart = scratch + 32;
for (int idx = tid; idx < m * sub; idx += nt) {
int r = idx / sub, c = idx % sub;
sp[r * ld + c] = Ab[(long)(koff + r) * n + (koff + c)];
}
__syncthreads();
for (int jj = 0; jj < sub; ++jj) {
float x0 = sp[jj * ld + jj];
float loc = 0.0f;
for (int r = jj + 1 + tid; r < m; r += nt) {
float v = sp[r * ld + jj];
loc += v * v;
}
float xtail2 = blockReduceSum(loc, scratch);
float beta, tauv, inv;
if (xtail2 <= 1.17549435e-38f) {
beta = x0; tauv = 0.0f; inv = 0.0f;
} else {
float nrm = sqrtf(x0 * x0 + xtail2);
beta = (x0 >= 0.0f) ? -nrm : nrm;
tauv = (beta - x0) / beta;
inv = 1.0f / (x0 - beta);
}
if (tid == 0) {
sp[jj * ld + jj] = beta;
tb[koff + jj] = tauv;
}
if (jj + 1 < sub && tauv != 0.0f) {
int ncol = sub - jj - 1;
float wl[32];
#pragma unroll
for (int c = 0; c < 32; ++c) wl[c] = 0.0f;
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : (sp[r * ld + jj] * inv);
const float* row = &sp[r * ld + jj + 1];
#pragma unroll
for (int c = 0; c < 32; ++c) if (c < ncol) wl[c] += vr * row[c];
}
#pragma unroll
for (int c = 0; c < 32; ++c) {
if (c >= ncol) break;
float val = wl[c];
for (int o = 16; o > 0; o >>= 1) val += __shfl_down_sync(0xffffffff, val, o);
if (lane == 0) wpart[warp * 32 + c] = val;
}
__syncthreads();
float wreg[32];
#pragma unroll
for (int c = 0; c < 32; ++c) {
if (c >= ncol) break;
float acc = 0.0f;
for (int p = 0; p < nw; ++p) acc += wpart[p * 32 + c];
wreg[c] = tauv * acc;
}
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : (sp[r * ld + jj] * inv);
float* row = &sp[r * ld + jj + 1];
#pragma unroll
for (int c = 0; c < 32; ++c) if (c < ncol) row[c] -= vr * wreg[c];
if (r > jj) sp[r * ld + jj] = vr;
}
__syncthreads();
} else {
for (int r = jj + 1 + tid; r < m; r += nt) sp[r * ld + jj] *= inv;
__syncthreads();
}
}
for (int idx = tid; idx < m * sub; idx += nt) {
int r = idx / sub, c = idx % sub;
Ab[(long)(koff + r) * n + (koff + c)] = sp[r * ld + c];
}
__syncthreads();
}
int N = 64 - (q + 1) * sub;
if (N <= 0) continue;
{
float* V = smem;
float* G = V + (long)m * sub;
float* Tm = G + sub * sub;
float* Wm = Tm + sub * sub;
float* Ym = Wm + sub * N;
float* Cbase = Ab + (long)koff * n + (koff + sub);
for (int idx = tid; idx < m * sub; idx += nt) {
int r = idx / sub, c = idx % sub;
float v = Ab[(long)(koff + r) * n + (koff + c)];
V[idx] = (r > c) ? v : (r == c ? 1.0f : 0.0f);
}
__syncthreads();
for (int idx = tid; idx < sub * sub; idx += nt) {
int i = idx / sub, j = idx % sub;
if (i <= j) {
float s = 0.0f;
for (int r = 0; r < m; ++r) s += V[r * sub + i] * V[r * sub + j];
G[i * sub + j] = s; G[j * sub + i] = s;
}
}
__syncthreads();
for (int jc = tid; jc < sub; jc += nt) {
for (int i = 0; i < sub; ++i) Tm[i * sub + jc] = 0.0f;
float mjj = (tb[koff + jc] != 0.0f) ? (1.0f / tb[koff + jc]) : 1.0e30f;
Tm[jc * sub + jc] = 1.0f / mjj;
for (int i = jc + 1; i < sub; ++i) {
float s = 0.0f;
for (int kk = jc; kk < i; ++kk) {
float mik = (i == kk) ? mjj : G[i * sub + kk];
s += mik * Tm[kk * sub + jc];
}
float mii = (tb[koff + i] != 0.0f) ? (1.0f / tb[koff + i]) : 1.0e30f;
Tm[i * sub + jc] = -s / mii;
}
}
__syncthreads();
int sub_tiles = 1;
int N_tiles_n = (N + N16 - 1) / N16;
int m_tiles = (m + M16 - 1) / M16;
for (int t = warp; t < sub_tiles * N_tiles_n; t += nw) {
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16;
int mv = (mt < sub), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < m; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::col_major> a;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bb;
if (mv) wmma::load_matrix_sync(a, V + kk * sub + mt, sub);
else for (int i = 0; i < a.num_elements; ++i) a.x[i] = 0.0f;
if (nv) wmma::load_matrix_sync(bb, Cbase + (long)kk * n + nt0, n);
else for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = 0.0f;
for (int i = 0; i < a.num_elements; ++i) a.x[i] = wmma::__float_to_tf32(a.x[i]);
for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = wmma::__float_to_tf32(bb.x[i]);
wmma::mma_sync(acc, a, bb, acc);
}
if (mv && nv) wmma::store_matrix_sync(Wm + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < sub_tiles * N_tiles_n; t += nw) {
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16;
int mv = (mt < sub), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < sub; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> a;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bb;
if (mv) wmma::load_matrix_sync(a, Tm + mt * sub + kk, sub);
else for (int i = 0; i < a.num_elements; ++i) a.x[i] = 0.0f;
if (nv) wmma::load_matrix_sync(bb, Wm + kk * N + nt0, N);
else for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = 0.0f;
for (int i = 0; i < a.num_elements; ++i) a.x[i] = wmma::__float_to_tf32(a.x[i]);
for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = wmma::__float_to_tf32(bb.x[i]);
wmma::mma_sync(acc, a, bb, acc);
}
if (mv && nv) wmma::store_matrix_sync(Ym + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < m_tiles * N_tiles_n; t += nw) {
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16;
int mv = (mt < m), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < sub; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> a;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bb;
if (mv) wmma::load_matrix_sync(a, V + mt * sub + kk, sub);
else for (int i = 0; i < a.num_elements; ++i) a.x[i] = 0.0f;
if (nv) wmma::load_matrix_sync(bb, Ym + kk * N + nt0, N);
else for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = 0.0f;
for (int i = 0; i < a.num_elements; ++i) a.x[i] = wmma::__float_to_tf32(a.x[i]);
for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = wmma::__float_to_tf32(bb.x[i]);
wmma::mma_sync(acc, a, bb, acc);
}
if (mv && nv) {
wmma::fragment<wmma::accumulator, M16, N16, K8, float> cf;
wmma::load_matrix_sync(cf, Cbase + (long)mt * n + nt0, n, wmma::mem_row_major);
for (int i = 0; i < acc.num_elements; ++i) acc.x[i] = cf.x[i] - acc.x[i];
wmma::store_matrix_sync(Cbase + (long)mt * n + nt0, acc, n, wmma::mem_row_major);
}
}
__syncthreads();
}
}
}
void panel64_fused(torch::Tensor A, torch::Tensor tau, int64_t k0) {
int B = A.size(0), n = A.size(1);
int m = n - (int)k0;
int threads = (B <= 128) ? 256 : 128;
int nw = (threads + 31) / 32;
size_t smem_factor = (size_t)((long)m * 17 + 32 + nw * 32) * sizeof(float);
size_t smem_wy = (size_t)((long)m * 16 + 2 * 16 * 16 + 2 * 16 * 48) * sizeof(float);
size_t smem = smem_factor > smem_wy ? smem_factor : smem_wy;
cudaError_t e = cudaFuncSetAttribute(panel64_fused_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
TORCH_CHECK(e == cudaSuccess, "smem attr(panel64_fused): ", cudaGetErrorString(e), " smem=", smem);
panel64_fused_kernel<<<B, threads, smem>>>(A.data_ptr<float>(), tau.data_ptr<float>(), B, n, (int)k0);
e = cudaGetLastError();
TORCH_CHECK(e == cudaSuccess, "panel64_fused launch: ", cudaGetErrorString(e), " smem=", smem);
}
__global__ void panel64_fused_3x_kernel(float* __restrict__ A, float* __restrict__ tau,
int B, int n, int k0) {
int b = blockIdx.x; if (b >= B) return;
float* Ab = A + (long)b * n * n;
float* tb = tau + (long)b * n;
extern __shared__ float smem[];
int tid = threadIdx.x, nt = blockDim.x;
int lane = tid & 31, warp = tid >> 5, nw = (nt + 31) >> 5;
const int sub = 16;
const int ld = 17;
for (int q = 0; q < 4; ++q) {
int koff = k0 + q * sub;
int m = n - koff;
{
float* sp = smem;
float* scratch = sp + (long)m * ld;
float* wpart = scratch + 32;
for (int idx = tid; idx < m * sub; idx += nt) {
int r = idx / sub, c = idx % sub;
sp[r * ld + c] = Ab[(long)(koff + r) * n + (koff + c)];
}
__syncthreads();
for (int jj = 0; jj < sub; ++jj) {
float x0 = sp[jj * ld + jj];
float loc = 0.0f;
for (int r = jj + 1 + tid; r < m; r += nt) {
float v = sp[r * ld + jj];
loc += v * v;
}
float xtail2 = blockReduceSum(loc, scratch);
float beta, tauv, inv;
if (xtail2 <= 1.17549435e-38f) {
beta = x0; tauv = 0.0f; inv = 0.0f;
} else {
float nrm = sqrtf(x0 * x0 + xtail2);
beta = (x0 >= 0.0f) ? -nrm : nrm;
tauv = (beta - x0) / beta;
inv = 1.0f / (x0 - beta);
}
if (tid == 0) {
sp[jj * ld + jj] = beta;
tb[koff + jj] = tauv;
}
if (jj + 1 < sub && tauv != 0.0f) {
int ncol = sub - jj - 1;
float wl[32];
#pragma unroll
for (int c = 0; c < 32; ++c) wl[c] = 0.0f;
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : (sp[r * ld + jj] * inv);
const float* row = &sp[r * ld + jj + 1];
#pragma unroll
for (int c = 0; c < 32; ++c) if (c < ncol) wl[c] += vr * row[c];
}
#pragma unroll
for (int c = 0; c < 32; ++c) {
if (c >= ncol) break;
float val = wl[c];
for (int o = 16; o > 0; o >>= 1) val += __shfl_down_sync(0xffffffff, val, o);
if (lane == 0) wpart[warp * 32 + c] = val;
}
__syncthreads();
float wreg[32];
#pragma unroll
for (int c = 0; c < 32; ++c) {
if (c >= ncol) break;
float acc = 0.0f;
for (int p = 0; p < nw; ++p) acc += wpart[p * 32 + c];
wreg[c] = tauv * acc;
}
for (int r = jj + tid; r < m; r += nt) {
float vr = (r == jj) ? 1.0f : (sp[r * ld + jj] * inv);
float* row = &sp[r * ld + jj + 1];
#pragma unroll
for (int c = 0; c < 32; ++c) if (c < ncol) row[c] -= vr * wreg[c];
if (r > jj) sp[r * ld + jj] = vr;
}
__syncthreads();
} else {
for (int r = jj + 1 + tid; r < m; r += nt) sp[r * ld + jj] *= inv;
__syncthreads();
}
}
for (int idx = tid; idx < m * sub; idx += nt) {
int r = idx / sub, c = idx % sub;
Ab[(long)(koff + r) * n + (koff + c)] = sp[r * ld + c];
}
__syncthreads();
}
int N = 64 - (q + 1) * sub;
if (N <= 0) continue;
{
float* V = smem;
float* G = V + (long)m * sub;
float* Tm = G + sub * sub;
float* Wm = Tm + sub * sub;
float* Ym = Wm + sub * N;
float* Cbase = Ab + (long)koff * n + (koff + sub);
for (int idx = tid; idx < m * sub; idx += nt) {
int r = idx / sub, c = idx % sub;
float v = Ab[(long)(koff + r) * n + (koff + c)];
V[idx] = (r > c) ? v : (r == c ? 1.0f : 0.0f);
}
__syncthreads();
for (int idx = tid; idx < sub * sub; idx += nt) {
int i = idx / sub, j = idx % sub;
if (i <= j) {
float s = 0.0f;
for (int r = 0; r < m; ++r) s += V[r * sub + i] * V[r * sub + j];
G[i * sub + j] = s; G[j * sub + i] = s;
}
}
__syncthreads();
for (int jc = tid; jc < sub; jc += nt) {
for (int i = 0; i < sub; ++i) Tm[i * sub + jc] = 0.0f;
float mjj = (tb[koff + jc] != 0.0f) ? (1.0f / tb[koff + jc]) : 1.0e30f;
Tm[jc * sub + jc] = 1.0f / mjj;
for (int i = jc + 1; i < sub; ++i) {
float s = 0.0f;
for (int kk = jc; kk < i; ++kk) {
float mik = (i == kk) ? mjj : G[i * sub + kk];
s += mik * Tm[kk * sub + jc];
}
float mii = (tb[koff + i] != 0.0f) ? (1.0f / tb[koff + i]) : 1.0e30f;
Tm[i * sub + jc] = -s / mii;
}
}
__syncthreads();
int sub_tiles = 1;
int N_tiles_n = (N + N16 - 1) / N16;
int m_tiles = (m + M16 - 1) / M16;
for (int t = warp; t < sub_tiles * N_tiles_n; t += nw) {
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16;
int mv = (mt < sub), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < m; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::col_major> a, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bb, bl;
if (mv) wmma::load_matrix_sync(a, V + kk * sub + mt, sub);
else for (int i = 0; i < a.num_elements; ++i) a.x[i] = 0.0f;
if (nv) wmma::load_matrix_sync(bb, Cbase + (long)kk * n + nt0, n);
else for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = 0.0f;
if (true) {
for (int i = 0; i < a.num_elements; ++i) {
float v = a.x[i]; float hi = wmma::__float_to_tf32(v);
a.x[i] = hi; al.x[i] = wmma::__float_to_tf32(v - hi);
}
for (int i = 0; i < bb.num_elements; ++i) {
float v = bb.x[i]; float hi = wmma::__float_to_tf32(v);
bb.x[i] = hi; bl.x[i] = wmma::__float_to_tf32(v - hi);
}
wmma::mma_sync(acc, a, bb, acc);
wmma::mma_sync(acc, a, bl, acc);
wmma::mma_sync(acc, al, bb, acc);
} else {
for (int i = 0; i < a.num_elements; ++i) a.x[i] = wmma::__float_to_tf32(a.x[i]);
for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = wmma::__float_to_tf32(bb.x[i]);
wmma::mma_sync(acc, a, bb, acc);
}
}
if (mv && nv) wmma::store_matrix_sync(Wm + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < sub_tiles * N_tiles_n; t += nw) {
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16;
int mv = (mt < sub), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < sub; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> a, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bb, bl;
if (mv) wmma::load_matrix_sync(a, Tm + mt * sub + kk, sub);
else for (int i = 0; i < a.num_elements; ++i) a.x[i] = 0.0f;
if (nv) wmma::load_matrix_sync(bb, Wm + kk * N + nt0, N);
else for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = 0.0f;
if (true) {
for (int i = 0; i < a.num_elements; ++i) {
float v = a.x[i]; float hi = wmma::__float_to_tf32(v);
a.x[i] = hi; al.x[i] = wmma::__float_to_tf32(v - hi);
}
for (int i = 0; i < bb.num_elements; ++i) {
float v = bb.x[i]; float hi = wmma::__float_to_tf32(v);
bb.x[i] = hi; bl.x[i] = wmma::__float_to_tf32(v - hi);
}
wmma::mma_sync(acc, a, bb, acc);
wmma::mma_sync(acc, a, bl, acc);
wmma::mma_sync(acc, al, bb, acc);
} else {
for (int i = 0; i < a.num_elements; ++i) a.x[i] = wmma::__float_to_tf32(a.x[i]);
for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = wmma::__float_to_tf32(bb.x[i]);
wmma::mma_sync(acc, a, bb, acc);
}
}
if (mv && nv) wmma::store_matrix_sync(Ym + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < m_tiles * N_tiles_n; t += nw) {
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16;
int mv = (mt < m), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < sub; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> a, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bb, bl;
if (mv) wmma::load_matrix_sync(a, V + mt * sub + kk, sub);
else for (int i = 0; i < a.num_elements; ++i) a.x[i] = 0.0f;
if (nv) wmma::load_matrix_sync(bb, Ym + kk * N + nt0, N);
else for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = 0.0f;
if (true) {
for (int i = 0; i < a.num_elements; ++i) {
float v = a.x[i]; float hi = wmma::__float_to_tf32(v);
a.x[i] = hi; al.x[i] = wmma::__float_to_tf32(v - hi);
}
for (int i = 0; i < bb.num_elements; ++i) {
float v = bb.x[i]; float hi = wmma::__float_to_tf32(v);
bb.x[i] = hi; bl.x[i] = wmma::__float_to_tf32(v - hi);
}
wmma::mma_sync(acc, a, bb, acc);
wmma::mma_sync(acc, a, bl, acc);
wmma::mma_sync(acc, al, bb, acc);
} else {
for (int i = 0; i < a.num_elements; ++i) a.x[i] = wmma::__float_to_tf32(a.x[i]);
for (int i = 0; i < bb.num_elements; ++i) bb.x[i] = wmma::__float_to_tf32(bb.x[i]);
wmma::mma_sync(acc, a, bb, acc);
}
}
if (mv && nv) {
wmma::fragment<wmma::accumulator, M16, N16, K8, float> cf;
wmma::load_matrix_sync(cf, Cbase + (long)mt * n + nt0, n, wmma::mem_row_major);
for (int i = 0; i < acc.num_elements; ++i) acc.x[i] = cf.x[i] - acc.x[i];
wmma::store_matrix_sync(Cbase + (long)mt * n + nt0, acc, n, wmma::mem_row_major);
}
}
__syncthreads();
}
}
}
void panel64_fused_3x(torch::Tensor A, torch::Tensor tau, int64_t k0) {
int B = A.size(0), n = A.size(1);
int m = n - (int)k0;
int threads = (B <= 128) ? 256 : 128;
int nw = (threads + 31) / 32;
size_t smem_factor = (size_t)((long)m * 17 + 32 + nw * 32) * sizeof(float);
size_t smem_wy = (size_t)((long)m * 16 + 2 * 16 * 16 + 2 * 16 * 48) * sizeof(float);
size_t smem = smem_factor > smem_wy ? smem_factor : smem_wy;
cudaError_t e = cudaFuncSetAttribute(panel64_fused_3x_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
TORCH_CHECK(e == cudaSuccess, "smem attr(panel64_fused): ", cudaGetErrorString(e), " smem=", smem);
panel64_fused_3x_kernel<<<B, threads, smem>>>(A.data_ptr<float>(), tau.data_ptr<float>(), B, n, (int)k0);
e = cudaGetLastError();
TORCH_CHECK(e == cudaSuccess, "panel64_fused launch: ", cudaGetErrorString(e), " smem=", smem);
}
// 3xTF32 FP32-accurate WY (larfb) on tensor cores -- for the FP32-stuck mixed shapes.
// Each wmma GEMM loads FP32 once, splits each fragment into tf32 hi+lo, does 3 mma_sync
// (hi*hi + hi*lo + lo*hi). Same smem traffic, 3x MMA (hidden behind latency-bound narrow-K).
__global__ void wy_apply_3x_kernel(float* __restrict__ A, const float* __restrict__ tau,
int B, int n, int koff, int sub, int N) {
int b = blockIdx.x; if (b >= B) return;
float* Ab = A + (long)b * n * n;
const float* tb = tau + (long)b * n + koff;
int mrows = n - koff;
extern __shared__ float sh[];
float* V = sh; float* G = V + (long)mrows * sub; float* Tm = G + sub * sub;
float* Wm = Tm + sub * sub; float* Ym = Wm + sub * N;
float* Cbase = Ab + (long)koff * n + (koff + sub);
int tid = threadIdx.x, nt = blockDim.x, warp = tid >> 5, nw = nt >> 5;
for (int idx = tid; idx < mrows * sub; idx += nt) { int r = idx / sub, c = idx % sub;
float v = Ab[(long)(koff + r) * n + (koff + c)]; V[idx] = (r > c) ? v : (r == c ? 1.0f : 0.0f); }
__syncthreads();
for (int idx = tid; idx < sub * sub; idx += nt) { int i = idx / sub, j = idx % sub;
if (i <= j) { float s = 0.0f; for (int r = 0; r < mrows; ++r) s += V[r * sub + i] * V[r * sub + j];
G[i * sub + j] = s; G[j * sub + i] = s; } }
__syncthreads();
for (int jc = tid; jc < sub; jc += nt) {
for (int i = 0; i < sub; ++i) Tm[i * sub + jc] = 0.0f;
float mjj = (tb[jc] != 0.0f) ? (1.0f / tb[jc]) : 1.0e30f;
Tm[jc * sub + jc] = 1.0f / mjj;
for (int i = jc + 1; i < sub; ++i) { float s = 0.0f;
for (int kk = jc; kk < i; ++kk) { float mik = (i == kk) ? mjj : G[i * sub + kk]; s += mik * Tm[kk * sub + jc]; }
float mii = (tb[i] != 0.0f) ? (1.0f / tb[i]) : 1.0e30f; Tm[i * sub + jc] = -s / mii; }
}
__syncthreads();
int sub_tiles = (sub + M16 - 1) / M16, N_tiles_n = (N + N16 - 1) / N16, m_tiles = (mrows + M16 - 1) / M16;
for (int t = warp; t < sub_tiles * N_tiles_n; t += nw) { // W = V^T C
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16; int mv = (mt < sub), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc; wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < mrows; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::col_major> ah, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bh, bl;
if (mv) wmma::load_matrix_sync(ah, V + kk * sub + mt, sub); else for (int i=0;i<ah.num_elements;++i) ah.x[i]=0.0f;
if (nv) wmma::load_matrix_sync(bh, Cbase + (long)kk * n + nt0, n); else for (int i=0;i<bh.num_elements;++i) bh.x[i]=0.0f;
for (int i=0;i<ah.num_elements;++i){ float v=ah.x[i]; float hi=wmma::__float_to_tf32(v); ah.x[i]=hi; al.x[i]=wmma::__float_to_tf32(v-hi);}
for (int i=0;i<bh.num_elements;++i){ float v=bh.x[i]; float hi=wmma::__float_to_tf32(v); bh.x[i]=hi; bl.x[i]=wmma::__float_to_tf32(v-hi);}
wmma::mma_sync(acc, ah, bh, acc); wmma::mma_sync(acc, ah, bl, acc); wmma::mma_sync(acc, al, bh, acc);
}
if (mv && nv) wmma::store_matrix_sync(Wm + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < sub_tiles * N_tiles_n; t += nw) { // Y = T W
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16; int mv = (mt < sub), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc; wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < sub; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> ah, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bh, bl;
if (mv) wmma::load_matrix_sync(ah, Tm + mt * sub + kk, sub); else for (int i=0;i<ah.num_elements;++i) ah.x[i]=0.0f;
if (nv) wmma::load_matrix_sync(bh, Wm + kk * N + nt0, N); else for (int i=0;i<bh.num_elements;++i) bh.x[i]=0.0f;
for (int i=0;i<ah.num_elements;++i){ float v=ah.x[i]; float hi=wmma::__float_to_tf32(v); ah.x[i]=hi; al.x[i]=wmma::__float_to_tf32(v-hi);}
for (int i=0;i<bh.num_elements;++i){ float v=bh.x[i]; float hi=wmma::__float_to_tf32(v); bh.x[i]=hi; bl.x[i]=wmma::__float_to_tf32(v-hi);}
wmma::mma_sync(acc, ah, bh, acc); wmma::mma_sync(acc, ah, bl, acc); wmma::mma_sync(acc, al, bh, acc);
}
if (mv && nv) wmma::store_matrix_sync(Ym + mt * N + nt0, acc, N, wmma::mem_row_major);
}
__syncthreads();
for (int t = warp; t < m_tiles * N_tiles_n; t += nw) { // C -= V Y
int mt = (t / N_tiles_n) * M16, nt0 = (t % N_tiles_n) * N16; int mv = (mt < mrows), nv = (nt0 < N);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc; wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < sub; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> ah, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bh, bl;
if (mv) wmma::load_matrix_sync(ah, V + mt * sub + kk, sub); else for (int i=0;i<ah.num_elements;++i) ah.x[i]=0.0f;
if (nv) wmma::load_matrix_sync(bh, Ym + kk * N + nt0, N); else for (int i=0;i<bh.num_elements;++i) bh.x[i]=0.0f;
for (int i=0;i<ah.num_elements;++i){ float v=ah.x[i]; float hi=wmma::__float_to_tf32(v); ah.x[i]=hi; al.x[i]=wmma::__float_to_tf32(v-hi);}
for (int i=0;i<bh.num_elements;++i){ float v=bh.x[i]; float hi=wmma::__float_to_tf32(v); bh.x[i]=hi; bl.x[i]=wmma::__float_to_tf32(v-hi);}
wmma::mma_sync(acc, ah, bh, acc); wmma::mma_sync(acc, ah, bl, acc); wmma::mma_sync(acc, al, bh, acc);
}
if (mv && nv) { wmma::fragment<wmma::accumulator, M16, N16, K8, float> cf;
wmma::load_matrix_sync(cf, Cbase + (long)mt * n + nt0, n, wmma::mem_row_major);
for (int i = 0; i < acc.num_elements; ++i) acc.x[i] = cf.x[i] - acc.x[i];
wmma::store_matrix_sync(Cbase + (long)mt * n + nt0, acc, n, wmma::mem_row_major); }
}
}
void wy_apply_3x(torch::Tensor A, torch::Tensor tau, int64_t koff, int64_t sub, int64_t N) {
int B = A.size(0), n = A.size(1); int mrows = n - (int)koff;
size_t smem = (size_t)((long)mrows * sub + 2 * sub * sub + 2 * sub * N) * sizeof(float);
cudaFuncSetAttribute(wy_apply_3x_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
wy_apply_3x_kernel<<<B, 256, smem>>>(A.data_ptr<float>(), tau.data_ptr<float>(), B, n, (int)koff, (int)sub, (int)N);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "wy_apply_3x: ", cudaGetErrorString(e), " smem=", smem);
}
// v304: batched lower-triangular inverse. M = strictly-lower(G) + diag(1/tau), T=M^{-1}.
// Replaces solve_triangular + where/diagonal setup. G = V^T V symmetric gram (cuBLAS);
// solve_triangular(S^T,eye) == inv(tril(S)) since S is symmetric w/ the 1/tau diagonal.
// One block/matrix; T columns independent (each thread inverts one column by forward sub).
__global__ void trtri_kernel(const float* __restrict__ G, const float* __restrict__ tau,
float* __restrict__ T, int B, int jb, int koff, int n) {
int b = blockIdx.x; if (b >= B) return;
const float* Gb = G + (long)b * jb * jb;
const float* tb = tau + (long)b * n + koff;
float* Tb = T + (long)b * jb * jb;
extern __shared__ float sh[];
float* Ls = sh; // jb*jb (lower-tri M)
float* Ts = Ls + (long)jb * jb; // jb*jb (inverse)
int tid = threadIdx.x, nt = blockDim.x;
for (int idx = tid; idx < jb * jb; idx += nt) {
int i = idx / jb, j = idx % jb;
float v;
if (i > j) v = Gb[i * jb + j];
else if (i == j) { float t = tb[i]; v = (t != 0.0f) ? (1.0f / t) : 1.0e30f; }
else v = 0.0f;
Ls[idx] = v; Ts[idx] = 0.0f;
}
__syncthreads();
for (int j = tid; j < jb; j += nt) {
float djj = 1.0f / Ls[j * jb + j];
Ts[j * jb + j] = djj;
for (int i = j + 1; i < jb; ++i) {
float s = 0.0f;
for (int kk = j; kk < i; ++kk) s += Ls[i * jb + kk] * Ts[kk * jb + j];
Ts[i * jb + j] = -s / Ls[i * jb + i];
}
}
__syncthreads();
for (int idx = tid; idx < jb * jb; idx += nt) Tb[idx] = Ts[idx];
}
void trtri(torch::Tensor G, torch::Tensor tau, torch::Tensor T, int64_t koff) {
int B = G.size(0), jb = G.size(1), n = tau.size(1);
size_t smem = (size_t)(2 * jb * jb) * sizeof(float);
int th = jb <= 64 ? 64 : 128;
cudaFuncSetAttribute(trtri_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
trtri_kernel<<<B, th, smem>>>(G.data_ptr<float>(), tau.data_ptr<float>(), T.data_ptr<float>(), B, jb, (int)koff, n);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "trtri: ", cudaGetErrorString(e));
}
__global__ void gram128_wmma3x_kernel(const float* __restrict__ X, float* __restrict__ G,
int B, int m) {
int ti = blockIdx.x, tj = blockIdx.y, b = blockIdx.z;
if (b >= B) return;
const float* Xb = X + (long)b * m * 128;
float* Gb = G + (long)b * 128 * 128;
int i0 = ti * 16, j0 = tj * 16;
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < m; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::col_major> ah, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bh, bl;
wmma::load_matrix_sync(ah, Xb + (long)kk * 128 + i0, 128);
wmma::load_matrix_sync(bh, Xb + (long)kk * 128 + j0, 128);
for (int i = 0; i < ah.num_elements; ++i) {
float v = ah.x[i];
float hi = wmma::__float_to_tf32(v);
ah.x[i] = hi;
al.x[i] = wmma::__float_to_tf32(v - hi);
}
for (int i = 0; i < bh.num_elements; ++i) {
float v = bh.x[i];
float hi = wmma::__float_to_tf32(v);
bh.x[i] = hi;
bl.x[i] = wmma::__float_to_tf32(v - hi);
}
wmma::mma_sync(acc, ah, bh, acc);
wmma::mma_sync(acc, ah, bl, acc);
wmma::mma_sync(acc, al, bh, acc);
}
wmma::store_matrix_sync(Gb + i0 * 128 + j0, acc, 128, wmma::mem_row_major);
}
__global__ void gram128_wmma3x_splitk_kernel(const float* __restrict__ X,
float* __restrict__ P,
int B, int m, int splitK) {
int ti = blockIdx.x, tj = blockIdx.y;
int bz = blockIdx.z;
int b = bz / splitK;
int sk = bz - b * splitK;
if (b >= B) return;
const float* Xb = X + (long)b * m * 128;
float* Pb = P + ((long)b * splitK + sk) * 128 * 128;
int i0 = ti * 16, j0 = tj * 16;
int chunk = ((m + splitK - 1) / splitK + 7) & ~7;
int kbeg = sk * chunk;
int kend = min(m, kbeg + chunk);
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = kbeg; kk < kend; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::col_major> ah, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bh, bl;
wmma::load_matrix_sync(ah, Xb + (long)kk * 128 + i0, 128);
wmma::load_matrix_sync(bh, Xb + (long)kk * 128 + j0, 128);
for (int i = 0; i < ah.num_elements; ++i) {
float v = ah.x[i];
float hi = wmma::__float_to_tf32(v);
ah.x[i] = hi;
al.x[i] = wmma::__float_to_tf32(v - hi);
}
for (int i = 0; i < bh.num_elements; ++i) {
float v = bh.x[i];
float hi = wmma::__float_to_tf32(v);
bh.x[i] = hi;
bl.x[i] = wmma::__float_to_tf32(v - hi);
}
wmma::mma_sync(acc, ah, bh, acc);
wmma::mma_sync(acc, ah, bl, acc);
wmma::mma_sync(acc, al, bh, acc);
}
wmma::store_matrix_sync(Pb + i0 * 128 + j0, acc, 128, wmma::mem_row_major);
}
__global__ void gram128_splitk_reduce_kernel(const float* __restrict__ P,
float* __restrict__ G,
int B, int splitK) {
int ti = blockIdx.x, tj = blockIdx.y, b = blockIdx.z;
if (b >= B) return;
int tid = threadIdx.x;
int i0 = ti * 16, j0 = tj * 16;
int r = tid >> 4;
int c = tid & 15;
float s = 0.0f;
for (int sk = 0; sk < splitK; ++sk) {
const float* Pb = P + ((long)b * splitK + sk) * 128 * 128;
s += Pb[(i0 + r) * 128 + (j0 + c)];
}
float* Gb = G + (long)b * 128 * 128;
Gb[(i0 + r) * 128 + (j0 + c)] = s;
}
__global__ void gram128_splitk_equil_reduce_kernel(const float* __restrict__ P,
float* __restrict__ G,
float* __restrict__ cn,
int B, int splitK) {
int ti = blockIdx.x, tj = blockIdx.y, b = blockIdx.z;
if (b >= B) return;
int tid = threadIdx.x;
int i0 = ti * 16, j0 = tj * 16;
int r = tid >> 4;
int c = tid & 15;
int i = i0 + r;
int j = j0 + c;
float s = 0.0f;
float ni = 0.0f;
float nj = 0.0f;
for (int sk = 0; sk < splitK; ++sk) {
const float* Pb = P + ((long)b * splitK + sk) * 128 * 128;
s += Pb[i * 128 + j];
ni += Pb[i * 128 + i];
nj += Pb[j * 128 + j];
}
ni = fmaxf(ni, 1.0e-30f);
nj = fmaxf(nj, 1.0e-30f);
float* Gb = G + (long)b * 128 * 128;
Gb[i * 128 + j] = s * rsqrtf(ni) * rsqrtf(nj);
if (ti == tj && r == c) cn[(long)b * 128 + i] = sqrtf(ni);
}
void gram128_wmma3x(torch::Tensor X, torch::Tensor G) {
int B = X.size(0), m = X.size(1);
TORCH_CHECK(X.size(2) == 128 && G.size(1) == 128 && G.size(2) == 128, "gram128_wmma3x expects jb=128");
TORCH_CHECK((m % 8) == 0, "gram128_wmma3x expects m multiple of 8");
dim3 grid(8, 8, B);
gram128_wmma3x_kernel<<<grid, 32>>>(X.data_ptr<float>(), G.data_ptr<float>(), B, m);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "gram128_wmma3x: ", cudaGetErrorString(e));
}
void gram128_wmma3x_splitk(torch::Tensor X, torch::Tensor G, torch::Tensor P, int64_t splitK64) {
int B = X.size(0), m = X.size(1), splitK = (int)splitK64;
TORCH_CHECK(X.size(2) == 128 && G.size(1) == 128 && G.size(2) == 128, "gram128_wmma3x_splitk expects jb=128");
TORCH_CHECK(P.size(0) == B && P.size(1) == splitK && P.size(2) == 128 && P.size(3) == 128,
"gram128_wmma3x_splitk partial shape mismatch");
TORCH_CHECK((m % 8) == 0 && splitK >= 1 && splitK <= 16, "gram128_wmma3x_splitk bad m/splitK");
dim3 grid_partial(8, 8, B * splitK);
gram128_wmma3x_splitk_kernel<<<grid_partial, 32>>>(X.data_ptr<float>(), P.data_ptr<float>(), B, m, splitK);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "gram128_wmma3x_splitk partial: ", cudaGetErrorString(e));
dim3 grid_reduce(8, 8, B);
gram128_splitk_reduce_kernel<<<grid_reduce, 256>>>(P.data_ptr<float>(), G.data_ptr<float>(), B, splitK);
e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "gram128_wmma3x_splitk reduce: ", cudaGetErrorString(e));
}
void gram128_wmma3x_splitk_equil(torch::Tensor X, torch::Tensor G, torch::Tensor P, torch::Tensor cn, int64_t splitK64) {
int B = X.size(0), m = X.size(1), splitK = (int)splitK64;
TORCH_CHECK(X.size(2) == 128 && G.size(1) == 128 && G.size(2) == 128, "gram128_wmma3x_splitk_equil expects jb=128");
TORCH_CHECK(P.size(0) == B && P.size(1) == splitK && P.size(2) == 128 && P.size(3) == 128,
"gram128_wmma3x_splitk_equil partial shape mismatch");
TORCH_CHECK(cn.size(0) == B && cn.size(1) == 128, "gram128_wmma3x_splitk_equil cn shape mismatch");
TORCH_CHECK((m % 8) == 0 && splitK >= 1 && splitK <= 16, "gram128_wmma3x_splitk_equil bad m/splitK");
dim3 grid_partial(8, 8, B * splitK);
gram128_wmma3x_splitk_kernel<<<grid_partial, 32>>>(X.data_ptr<float>(), P.data_ptr<float>(), B, m, splitK);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "gram128_wmma3x_splitk_equil partial: ", cudaGetErrorString(e));
dim3 grid_reduce(8, 8, B);
gram128_splitk_equil_reduce_kernel<<<grid_reduce, 256>>>(
P.data_ptr<float>(), G.data_ptr<float>(), cn.data_ptr<float>(), B, splitK);
e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "gram128_wmma3x_splitk_equil reduce: ", cudaGetErrorString(e));
}
void panel_factor(torch::Tensor A, torch::Tensor tau, int64_t k, int64_t jb, int64_t threads) {
int B = A.size(0), n = A.size(1); int m = n - (int)k;
// v257: pad the panel smem row-stride to an odd ld (coprime with 32) so the
// sp[r*ld+jj] column accesses hit 32 distinct banks -> zero bank conflict
// (v256: bit-exact, ~0.72-0.78x panel time). ld = jb|1 is odd and >= jb.
int ld = (int)jb | 1;
// v254 dispatch: high batch saturates the GPU -> root block-sync kernel;
// low batch is under-occupied / latency-bound -> v253 fewer-syncs kernel.
if (B > 128 && n != 512) {
size_t smem = (size_t)((long)m * ld + 32 + jb + 3) * sizeof(float);
cudaError_t e = cudaFuncSetAttribute(panel_factor_kernel_root, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
TORCH_CHECK(e == cudaSuccess, "smem attr(root): ", cudaGetErrorString(e));
panel_factor_kernel_root<<<B, (int)threads, smem>>>(A.data_ptr<float>(), tau.data_ptr<float>(), B, n, (int)k, (int)jb, ld);
e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "panel launch(root): ", cudaGetErrorString(e));
} else {
int nw = ((int)threads + 31) / 32; // wpart holds nw partial w-vectors of width 32
size_t smem = (size_t)((long)m * ld + 32 + nw * 32) * sizeof(float);
cudaError_t e = cudaFuncSetAttribute(panel_factor_kernel_fewsync, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
TORCH_CHECK(e == cudaSuccess, "smem attr(fewsync): ", cudaGetErrorString(e));
panel_factor_kernel_fewsync<<<B, (int)threads, smem>>>(A.data_ptr<float>(), tau.data_ptr<float>(), B, n, (int)k, (int)jb, ld);
e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "panel launch(fewsync): ", cudaGetErrorString(e));
}
}
void m2_larfb(torch::Tensor V, torch::Tensor T, torch::Tensor C) {
int B = V.size(0), m = V.size(1), nb = V.size(2), N = C.size(2);
size_t bytes = (size_t)(m * nb + nb * nb + m * N + nb * N + nb * N) * sizeof(float);
cudaFuncSetAttribute(m2_larfb_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)bytes);
m2_larfb_kernel<<<B, 256, bytes>>>(V.data_ptr<float>(), T.data_ptr<float>(), C.data_ptr<float>(), B, m, nb, N);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "m2_larfb: ", cudaGetErrorString(e), " smem=", bytes);
}
void small_qr(torch::Tensor A, torch::Tensor tau) {
int B = A.size(0), n = A.size(1);
size_t smem = (size_t)((n * FNB) + 32 + FNB + 3 + (n * FTW)) * sizeof(float);
small_qr_kernel<<<B, 256, smem>>>(A.data_ptr<float>(), tau.data_ptr<float>(), B, n);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "small_qr: ", cudaGetErrorString(e));
}
// Warp-per-matrix QR for n<=32: one warp owns one matrix, lane r holds row r in registers, shfl
// reductions, ZERO block syncs (small_qr's ~96 syncs/matrix are pure overhead at this size).
__global__ void small_qr_warp_kernel(float* __restrict__ A, float* __restrict__ tau, int B, int n) {
int wid = (blockIdx.x * blockDim.x + threadIdx.x) >> 5; // global warp id = matrix id
if (wid >= B) return;
int lane = threadIdx.x & 31;
float* Ab = A + (long)wid * n * n; float* tb = tau + (long)wid * n;
float row[32];
#pragma unroll
for (int c = 0; c < 32; ++c) row[c] = (lane < n && c < n) ? Ab[(long)lane * n + c] : 0.0f;
for (int jj = 0; jj < n; ++jj) {
float myv = (lane >= jj + 1) ? row[jj] : 0.0f;
float xt2 = myv * myv;
#pragma unroll
for (int o = 16; o > 0; o >>= 1) xt2 += __shfl_down_sync(0xffffffff, xt2, o);
xt2 = __shfl_sync(0xffffffff, xt2, 0);
float x0 = __shfl_sync(0xffffffff, row[jj], jj);
float beta, tv, inv;
if (xt2 <= 1.17549435e-38f) { beta = x0; tv = 0.0f; inv = 0.0f; }
else { float nr = sqrtf(x0 * x0 + xt2); beta = (x0 >= 0.0f) ? -nr : nr; tv = (beta - x0) / beta; inv = 1.0f / (x0 - beta); }
float vr;
if (lane == jj) vr = 1.0f;
else if (lane > jj) { row[jj] = row[jj] * inv; vr = row[jj]; }
else vr = 0.0f;
if (lane == jj) { row[jj] = beta; tb[jj] = tv; }
if (tv != 0.0f) {
for (int c = jj + 1; c < n; ++c) {
float wc = vr * row[c];
#pragma unroll
for (int o = 16; o > 0; o >>= 1) wc += __shfl_down_sync(0xffffffff, wc, o);
wc = __shfl_sync(0xffffffff, wc, 0) * tv;
if (lane >= jj) row[c] = row[c] - vr * wc;
}
}
}
if (lane < n) {
#pragma unroll
for (int c = 0; c < 32; ++c) if (c < n) Ab[(long)lane * n + c] = row[c];
}
}
void small_qr_warp(torch::Tensor A, torch::Tensor tau) {
int B = A.size(0), n = A.size(1);
int threads = 256;
int blocks = (B * 32 + threads - 1) / threads;
small_qr_warp_kernel<<<blocks, threads>>>(A.data_ptr<float>(), tau.data_ptr<float>(), B, n);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "small_qr_warp: ", cudaGetErrorString(e));
}
__global__ void orhr_lu_kernel(const float* __restrict__ Q, float* __restrict__ Lbuf,
float* __restrict__ Uinvbuf, int B, int m, int ib) {
int b = blockIdx.x; if (b >= B) return;
const float* Qb = Q + (long)b * m * ib;
float* Lb = Lbuf + (long)b * ib * ib;
float* Ui = Uinvbuf + (long)b * ib * ib;
extern __shared__ float sm[];
float* M = sm;
float* Uinv = M + ib * ib;
int tid = threadIdx.x, nt = blockDim.x;
for (int i = tid; i < ib * ib; i += nt) {
int r = i / ib, c = i % ib;
M[i] = (r == c ? 1.0f : 0.0f) - Qb[r * ib + c];
Uinv[i] = 0.0f;
}
__syncthreads();
for (int k = 0; k < ib; ++k) {
float piv = M[k * ib + k];
for (int i = k + 1 + tid; i < ib; i += nt) M[i * ib + k] /= piv;
__syncthreads();
int rows = ib - k - 1;
for (int idx = tid; idx < rows * rows; idx += nt) {
int i = k + 1 + idx / rows;
int j = k + 1 + idx % rows;
M[i * ib + j] -= M[i * ib + k] * M[k * ib + j];
}
__syncthreads();
}
for (int i = tid; i < ib * ib; i += nt) {
int r = i / ib, c = i % ib;
Lb[i] = (r > c) ? M[i] : 0.0f;
}
if (tid < ib) {
int c = tid;
Uinv[c * ib + c] = 1.0f / M[c * ib + c];
for (int r = c - 1; r >= 0; --r) {
float s = 0.0f;
for (int t = r + 1; t <= c; ++t) s -= M[r * ib + t] * Uinv[t * ib + c];
Uinv[r * ib + c] = s / M[r * ib + r];
}
}
__syncthreads();
for (int i = tid; i < ib * ib; i += nt) Ui[i] = Uinv[i];
}
void orhr_lu(torch::Tensor Q, torch::Tensor Lbuf, torch::Tensor Uinvbuf) {
int B = Q.size(0), m = Q.size(1), ib = Q.size(2);
size_t smem = (size_t)(2 * ib * ib) * sizeof(float);
cudaError_t e = cudaFuncSetAttribute(orhr_lu_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
TORCH_CHECK(e == cudaSuccess, "orhr smem attr: ", cudaGetErrorString(e));
orhr_lu_kernel<<<B, 256, smem>>>(Q.data_ptr<float>(), Lbuf.data_ptr<float>(), Uinvbuf.data_ptr<float>(), B, m, ib);
e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "orhr launch: ", cudaGetErrorString(e));
}
__global__ void orhr_lu_signed_kernel(const float* __restrict__ Q, float* __restrict__ R,
float* __restrict__ Lbuf, float* __restrict__ Uinvbuf, int B, int m, int ib) {
int b = blockIdx.x; if (b >= B) return;
const float* Qb = Q + (long)b * m * ib;
float* Rb = R + (long)b * ib * ib;
float* Lb = Lbuf + (long)b * ib * ib;
float* Ui = Uinvbuf + (long)b * ib * ib;
extern __shared__ float sm[];
float* M = sm;
float* Uinv = M + ib * ib;
float* scales = Uinv + ib * ib;
int tid = threadIdx.x, nt = blockDim.x;
for (int j = tid; j < ib; j += nt) {
float d = Rb[j * ib + j];
scales[j] = (d < 0.0f) ? 1.0f : -1.0f;
}
__syncthreads();
for (int i = tid; i < ib * ib; i += nt) {
int r = i / ib, c = i % ib;
float sc = scales[c];
M[i] = (r == c ? 1.0f : 0.0f) - Qb[r * ib + c] * sc;
Uinv[i] = 0.0f;
Rb[i] *= scales[r];
}
__syncthreads();
for (int k = 0; k < ib; ++k) {
float piv = M[k * ib + k];
for (int i = k + 1 + tid; i < ib; i += nt) M[i * ib + k] /= piv;
__syncthreads();
int rows = ib - k - 1;
for (int idx = tid; idx < rows * rows; idx += nt) {
int i = k + 1 + idx / rows;
int j = k + 1 + idx % rows;
M[i * ib + j] -= M[i * ib + k] * M[k * ib + j];
}
__syncthreads();
}
for (int i = tid; i < ib * ib; i += nt) {
int r = i / ib, c = i % ib;
Lb[i] = (r > c) ? M[i] : 0.0f;
}
if (tid < ib) {
int c = tid;
Uinv[c * ib + c] = 1.0f / M[c * ib + c];
for (int r = c - 1; r >= 0; --r) {
float s = 0.0f;
for (int t = r + 1; t <= c; ++t) s -= M[r * ib + t] * Uinv[t * ib + c];
Uinv[r * ib + c] = s / M[r * ib + r];
}
}
__syncthreads();
for (int i = tid; i < ib * ib; i += nt) {
int r = i / ib;
Ui[i] = scales[r] * Uinv[i];
}
}
void orhr_lu_signed(torch::Tensor Q, torch::Tensor R, torch::Tensor Lbuf, torch::Tensor Uinvbuf) {
int B = Q.size(0), m = Q.size(1), ib = Q.size(2);
size_t smem = (size_t)(2 * ib * ib + ib) * sizeof(float);
cudaError_t e = cudaFuncSetAttribute(orhr_lu_signed_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, (int)smem);
TORCH_CHECK(e == cudaSuccess, "orhr signed smem attr: ", cudaGetErrorString(e));
orhr_lu_signed_kernel<<<B, 256, smem>>>(Q.data_ptr<float>(), R.data_ptr<float>(),
Lbuf.data_ptr<float>(), Uinvbuf.data_ptr<float>(), B, m, ib);
e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "orhr signed launch: ", cudaGetErrorString(e));
}
__global__ void orhr_finalize_tau_kernel(float* __restrict__ H,
const float* __restrict__ L, const float* __restrict__ R,
float* __restrict__ tau, int B, int m, int ib) {
int b = blockIdx.x;
int c = blockIdx.y;
if (b >= B || c >= ib) return;
float* Hb = H + (long)b * m * ib;
const float* Lb = L + (long)b * ib * ib;
const float* Rb = R + (long)b * ib * ib;
float s = (threadIdx.x == 0) ? 1.0f : 0.0f;
for (int r = threadIdx.x; r < ib; r += blockDim.x) {
float v = (r > c) ? Lb[r * ib + c] : Rb[r * ib + c];
Hb[r * ib + c] = v;
if (r > c) s += v * v;
}
for (int r = ib + threadIdx.x; r < m; r += blockDim.x) {
float v = Hb[(long)r * ib + c];
s += v * v;
}
extern __shared__ float scratch[];
int lane = threadIdx.x & 31;
int wid = threadIdx.x >> 5;
#pragma unroll
for (int o = 16; o > 0; o >>= 1) s += __shfl_down_sync(0xffffffff, s, o);
if (lane == 0) scratch[wid] = s;
__syncthreads();
int nw = (blockDim.x + 31) >> 5;
float total = (threadIdx.x < nw) ? scratch[lane] : 0.0f;
if (wid == 0) {
#pragma unroll
for (int o = 16; o > 0; o >>= 1) total += __shfl_down_sync(0xffffffff, total, o);
if (threadIdx.x == 0) tau[(long)b * ib + c] = 2.0f / fmaxf(total, 1.0e-30f);
}
}
void orhr_finalize_tau(torch::Tensor H, torch::Tensor L, torch::Tensor R, torch::Tensor tau) {
int B = H.size(0), m = H.size(1), ib = H.size(2);
int threads = 256;
int smem = ((threads + 31) / 32) * (int)sizeof(float);
orhr_finalize_tau_kernel<<<dim3(B, ib), threads, smem>>>(
H.data_ptr<float>(), L.data_ptr<float>(), R.data_ptr<float>(), tau.data_ptr<float>(), B, m, ib);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "orhr finalize: ", cudaGetErrorString(e));
}
__global__ void orhr_lower_tau_fused_kernel(const float* __restrict__ Q,
const float* __restrict__ L, const float* __restrict__ R,
const float* __restrict__ Uinv, float* __restrict__ H,
float* __restrict__ tau, int B, int m, int ib) {
int b = blockIdx.x;
int c = blockIdx.y;
if (b >= B || c >= ib) return;
const float* Qb = Q + (long)b * m * ib;
const float* Lb = L + (long)b * ib * ib;
const float* Rb = R + (long)b * ib * ib;
const float* Ui = Uinv + (long)b * ib * ib;
float* Hb = H + (long)b * m * ib;
float s = (threadIdx.x == 0) ? 1.0f : 0.0f;
for (int r = threadIdx.x; r < ib; r += blockDim.x) {
float v = (r > c) ? Lb[r * ib + c] : Rb[r * ib + c];
Hb[r * ib + c] = v;
if (r > c) s += v * v;
}
for (int r = ib + threadIdx.x; r < m; r += blockDim.x) {
float acc = 0.0f;
const float* qrow = Qb + (long)r * ib;
for (int k = 0; k < ib; ++k) acc += qrow[k] * Ui[k * ib + c];
float v = -acc;
Hb[(long)r * ib + c] = v;
s += v * v;
}
extern __shared__ float scratch[];
int lane = threadIdx.x & 31;
int wid = threadIdx.x >> 5;
#pragma unroll
for (int o = 16; o > 0; o >>= 1) s += __shfl_down_sync(0xffffffff, s, o);
if (lane == 0) scratch[wid] = s;
__syncthreads();
int nw = (blockDim.x + 31) >> 5;
float total = (threadIdx.x < nw) ? scratch[lane] : 0.0f;
if (wid == 0) {
#pragma unroll
for (int o = 16; o > 0; o >>= 1) total += __shfl_down_sync(0xffffffff, total, o);
if (threadIdx.x == 0) tau[(long)b * ib + c] = 2.0f / fmaxf(total, 1.0e-30f);
}
}
void orhr_lower_tau_fused(torch::Tensor Q, torch::Tensor L, torch::Tensor R,
torch::Tensor Uinv, torch::Tensor H, torch::Tensor tau) {
int B = H.size(0), m = H.size(1), ib = H.size(2);
int threads = 256;
int smem = ((threads + 31) / 32) * (int)sizeof(float);
orhr_lower_tau_fused_kernel<<<dim3(B, ib), threads, smem>>>(
Q.data_ptr<float>(), L.data_ptr<float>(), R.data_ptr<float>(), Uinv.data_ptr<float>(),
H.data_ptr<float>(), tau.data_ptr<float>(), B, m, ib);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "orhr lower/tau fused: ", cudaGetErrorString(e));
}
__global__ void orhr_lower_wmma3x_kernel(const float* __restrict__ Q,
const float* __restrict__ Uinv, float* __restrict__ H,
int B, int m, int ib) {
int rt = blockIdx.x;
int ct = blockIdx.y;
int b = blockIdx.z;
if (b >= B) return;
int r0 = ib + rt * M16;
int c0 = ct * N16;
const float* Qb = Q + (long)b * m * ib;
const float* Ui = Uinv + (long)b * ib * ib;
float* Hb = H + (long)b * m * ib;
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < ib; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> ah, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bh, bl;
wmma::load_matrix_sync(ah, Qb + (long)r0 * ib + kk, ib);
wmma::load_matrix_sync(bh, Ui + kk * ib + c0, ib);
for (int i = 0; i < ah.num_elements; ++i) {
float v = ah.x[i];
float hi = wmma::__float_to_tf32(v);
ah.x[i] = hi;
al.x[i] = wmma::__float_to_tf32(v - hi);
}
for (int i = 0; i < bh.num_elements; ++i) {
float v = bh.x[i];
float hi = wmma::__float_to_tf32(v);
bh.x[i] = hi;
bl.x[i] = wmma::__float_to_tf32(v - hi);
}
wmma::mma_sync(acc, ah, bh, acc);
wmma::mma_sync(acc, ah, bl, acc);
wmma::mma_sync(acc, al, bh, acc);
}
for (int i = 0; i < acc.num_elements; ++i) acc.x[i] = -acc.x[i];
wmma::store_matrix_sync(Hb + (long)r0 * ib + c0, acc, ib, wmma::mem_row_major);
}
void orhr_lower_wmma3x(torch::Tensor Q, torch::Tensor Uinv, torch::Tensor H) {
int B = H.size(0), m = H.size(1), ib = H.size(2);
int lower = m - ib;
if (lower <= 0) return;
TORCH_CHECK((ib % 16) == 0 && (lower % 16) == 0, "orhr lower wmma3x expects aligned CQR panel");
dim3 grid(lower / 16, ib / 16, B);
orhr_lower_wmma3x_kernel<<<grid, 32>>>(
Q.data_ptr<float>(), Uinv.data_ptr<float>(), H.data_ptr<float>(), B, m, ib);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "orhr lower wmma3x: ", cudaGetErrorString(e));
}
__global__ void orhr_top_tau_init_kernel(float* __restrict__ H,
const float* __restrict__ L, const float* __restrict__ R,
float* __restrict__ tau, int B, int m, int ib) {
int b = blockIdx.x;
int c = blockIdx.y;
if (b >= B || c >= ib) return;
float* Hb = H + (long)b * m * ib;
const float* Lb = L + (long)b * ib * ib;
const float* Rb = R + (long)b * ib * ib;
float s = (threadIdx.x == 0) ? 1.0f : 0.0f;
for (int r = threadIdx.x; r < ib; r += blockDim.x) {
float v = (r > c) ? Lb[r * ib + c] : Rb[r * ib + c];
Hb[r * ib + c] = v;
if (r > c) s += v * v;
}
extern __shared__ float scratch[];
int lane = threadIdx.x & 31;
int wid = threadIdx.x >> 5;
#pragma unroll
for (int o = 16; o > 0; o >>= 1) s += __shfl_down_sync(0xffffffff, s, o);
if (lane == 0) scratch[wid] = s;
__syncthreads();
int nw = (blockDim.x + 31) >> 5;
float total = (threadIdx.x < nw) ? scratch[lane] : 0.0f;
if (wid == 0) {
#pragma unroll
for (int o = 16; o > 0; o >>= 1) total += __shfl_down_sync(0xffffffff, total, o);
if (threadIdx.x == 0) tau[(long)b * ib + c] = total;
}
}
__global__ void orhr_lower_wmma3x_tau_kernel(const float* __restrict__ Q,
const float* __restrict__ Uinv, float* __restrict__ H,
float* __restrict__ tau, int B, int m, int ib) {
int rt = blockIdx.x;
int ct = blockIdx.y;
int b = blockIdx.z;
if (b >= B) return;
int r0 = ib + rt * M16;
int c0 = ct * N16;
const float* Qb = Q + (long)b * m * ib;
const float* Ui = Uinv + (long)b * ib * ib;
float* Hb = H + (long)b * m * ib;
wmma::fragment<wmma::accumulator, M16, N16, K8, float> acc;
wmma::fill_fragment(acc, 0.0f);
for (int kk = 0; kk < ib; kk += K8) {
wmma::fragment<wmma::matrix_a, M16, N16, K8, wmma::precision::tf32, wmma::row_major> ah, al;
wmma::fragment<wmma::matrix_b, M16, N16, K8, wmma::precision::tf32, wmma::row_major> bh, bl;
wmma::load_matrix_sync(ah, Qb + (long)r0 * ib + kk, ib);
wmma::load_matrix_sync(bh, Ui + kk * ib + c0, ib);
for (int i = 0; i < ah.num_elements; ++i) {
float v = ah.x[i];
float hi = wmma::__float_to_tf32(v);
ah.x[i] = hi;
al.x[i] = wmma::__float_to_tf32(v - hi);
}
for (int i = 0; i < bh.num_elements; ++i) {
float v = bh.x[i];
float hi = wmma::__float_to_tf32(v);
bh.x[i] = hi;
bl.x[i] = wmma::__float_to_tf32(v - hi);
}
wmma::mma_sync(acc, ah, bh, acc);
wmma::mma_sync(acc, ah, bl, acc);
wmma::mma_sync(acc, al, bh, acc);
}
for (int i = 0; i < acc.num_elements; ++i) acc.x[i] = -acc.x[i];
wmma::store_matrix_sync(Hb + (long)r0 * ib + c0, acc, ib, wmma::mem_row_major);
__syncwarp();
__shared__ float colsum[16];
int lane = threadIdx.x & 31;
if (lane < 16) colsum[lane] = 0.0f;
__syncwarp();
for (int idx = lane; idx < 256; idx += 32) {
int rr = idx >> 4;
int cc = idx & 15;
float v = Hb[(long)(r0 + rr) * ib + (c0 + cc)];
atomicAdd(&colsum[cc], v * v);
}
__syncwarp();
if (lane < 16) atomicAdd(tau + (long)b * ib + c0 + lane, colsum[lane]);
}
__global__ void orhr_tau_finish_kernel(float* __restrict__ tau, int total) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < total) tau[idx] = 2.0f / fmaxf(tau[idx], 1.0e-30f);
}
void orhr_top_tau_init(torch::Tensor H, torch::Tensor L, torch::Tensor R, torch::Tensor tau) {
int B = H.size(0), m = H.size(1), ib = H.size(2);
int threads = 256;
int smem = ((threads + 31) / 32) * (int)sizeof(float);
orhr_top_tau_init_kernel<<<dim3(B, ib), threads, smem>>>(
H.data_ptr<float>(), L.data_ptr<float>(), R.data_ptr<float>(), tau.data_ptr<float>(), B, m, ib);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "orhr top/tau init: ", cudaGetErrorString(e));
}
void orhr_lower_wmma3x_tau(torch::Tensor Q, torch::Tensor Uinv, torch::Tensor H, torch::Tensor tau) {
int B = H.size(0), m = H.size(1), ib = H.size(2);
int lower = m - ib;
if (lower <= 0) return;
TORCH_CHECK((ib % 16) == 0 && (lower % 16) == 0, "orhr lower wmma3x tau expects aligned CQR panel");
dim3 grid(lower / 16, ib / 16, B);
orhr_lower_wmma3x_tau_kernel<<<grid, 32>>>(
Q.data_ptr<float>(), Uinv.data_ptr<float>(), H.data_ptr<float>(), tau.data_ptr<float>(), B, m, ib);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "orhr lower wmma3x tau: ", cudaGetErrorString(e));
}
void orhr_tau_finish(torch::Tensor tau) {
int total = tau.numel();
int threads = 256;
int blocks = (total + threads - 1) / threads;
orhr_tau_finish_kernel<<<blocks, threads>>>(tau.data_ptr<float>(), total);
cudaError_t e = cudaGetLastError(); TORCH_CHECK(e == cudaSuccess, "orhr tau finish: ", cudaGetErrorString(e));
}
// Batched mixed-precision GEMM: C_fp32 = alpha * op(A_bf16) @ op(B_bf16) + beta * C_fp32.
// Inputs A,B are bf16 (CUDA_R_16BF); C is fp32 (CUDA_R_32F) and is accumulated in
// place with NO intermediate (beta applied directly to C). Compute type 32F.
// All tensors are row-major batched (B, rows, cols). M,N,K are the row-major
// (output M x N, contracted K) dims; transA/transB select op() on A/B. C may be a
// strided view (e.g. a sub-block of a larger matrix): its leading dim and batch
// stride are read from C.stride(), so C is never copied.
void mixed_bmm(torch::Tensor A, torch::Tensor B, torch::Tensor C,
int64_t M, int64_t N, int64_t K,
int64_t transA, int64_t transB, double alpha, double beta) {
TORCH_CHECK(A.scalar_type() == at::kBFloat16 && B.scalar_type() == at::kBFloat16,
"mixed_bmm: A,B must be bfloat16");
TORCH_CHECK(C.scalar_type() == at::kFloat, "mixed_bmm: C must be float32");
TORCH_CHECK(A.stride(2) == 1 && B.stride(2) == 1 && C.stride(2) == 1,
"mixed_bmm: last dim of A,B,C must be contiguous");
// Self-managed cuBLAS handle (created once). The borrowed torch handle
// is not valid in the eval-harness worker context on the B200 runner. The fresh
// handle defaults to the null launch queue, which is what we run on anyway.
static cublasHandle_t handle = nullptr;
if (!handle) {
cublasStatus_t cs = cublasCreate(&handle);
TORCH_CHECK(cs == CUBLAS_STATUS_SUCCESS, "cublasCreate failed: ", (int)cs);
}
float alphaf = (float)alpha, betaf = (float)beta;
cublasOperation_t opA = transA ? CUBLAS_OP_T : CUBLAS_OP_N;
cublasOperation_t opB = transB ? CUBLAS_OP_T : CUBLAS_OP_N;
int lda = (int)A.stride(1), ldb = (int)B.stride(1), ldc = (int)C.stride(1);
long long strideA = (long long)A.stride(0);
long long strideB = (long long)B.stride(0);
long long strideC = (long long)C.stride(0);
int batch = (int)A.size(0);
// cuBLAS is column-major: compute C^T = op(B)^T @ op(A)^T by swapping operands.
cublasStatus_t st = cublasGemmStridedBatchedEx(
handle, opB, opA,
(int)N, (int)M, (int)K,
&alphaf,
B.data_ptr(), CUDA_R_16BF, ldb, strideB,
A.data_ptr(), CUDA_R_16BF, lda, strideA,
&betaf,
C.data_ptr(), CUDA_R_32F, ldc, strideC,
batch, CUBLAS_COMPUTE_32F, CUBLAS_GEMM_DEFAULT);
TORCH_CHECK(st == CUBLAS_STATUS_SUCCESS, "mixed_bmm cublasGemmStridedBatchedEx failed: ", (int)st);
}
"""
_CPP = """
void panel_factor(torch::Tensor A, torch::Tensor tau, int64_t k, int64_t jb, int64_t threads);
void m2_larfb(torch::Tensor V, torch::Tensor T, torch::Tensor C);
void small_qr(torch::Tensor A, torch::Tensor tau);
void small_qr_warp(torch::Tensor A, torch::Tensor tau);
void trtri(torch::Tensor G, torch::Tensor tau, torch::Tensor T, int64_t koff);
void gram128_wmma3x(torch::Tensor X, torch::Tensor G);
void gram128_wmma3x_splitk(torch::Tensor X, torch::Tensor G, torch::Tensor P, int64_t splitK);
void gram128_wmma3x_splitk_equil(torch::Tensor X, torch::Tensor G, torch::Tensor P, torch::Tensor cn, int64_t splitK);
void wy_apply(torch::Tensor A, torch::Tensor tau, int64_t koff, int64_t sub, int64_t N);
void panel64_fused(torch::Tensor A, torch::Tensor tau, int64_t k0);
void panel64_fused_3x(torch::Tensor A, torch::Tensor tau, int64_t k0);
void wy_apply_3x(torch::Tensor A, torch::Tensor tau, int64_t koff, int64_t sub, int64_t N);
void orhr_lu(torch::Tensor Q, torch::Tensor Lbuf, torch::Tensor Uinvbuf);
void orhr_lu_signed(torch::Tensor Q, torch::Tensor R, torch::Tensor Lbuf, torch::Tensor Uinvbuf);
void orhr_finalize_tau(torch::Tensor H, torch::Tensor L, torch::Tensor R, torch::Tensor tau);
void orhr_lower_tau_fused(torch::Tensor Q, torch::Tensor L, torch::Tensor R, torch::Tensor Uinv, torch::Tensor H, torch::Tensor tau);
void orhr_lower_wmma3x(torch::Tensor Q, torch::Tensor Uinv, torch::Tensor H);
void orhr_top_tau_init(torch::Tensor H, torch::Tensor L, torch::Tensor R, torch::Tensor tau);
void orhr_lower_wmma3x_tau(torch::Tensor Q, torch::Tensor Uinv, torch::Tensor H, torch::Tensor tau);
void orhr_tau_finish(torch::Tensor tau);
void mixed_bmm(torch::Tensor A, torch::Tensor B, torch::Tensor C, int64_t M, int64_t N, int64_t K, int64_t transA, int64_t transB, double alpha, double beta);
"""
mod = load_inline(name="qr_n4096_bf16cublas_opt", cpp_sources=_CPP, cuda_sources=_CUDA,
functions=["panel_factor", "m2_larfb", "small_qr", "small_qr_warp", "trtri", "gram128_wmma3x", "gram128_wmma3x_splitk", "gram128_wmma3x_splitk_equil", "wy_apply", "panel64_fused", "panel64_fused_3x", "wy_apply_3x", "orhr_lu", "orhr_lu_signed", "orhr_finalize_tau", "orhr_lower_tau_fused", "orhr_lower_wmma3x", "orhr_top_tau_init", "orhr_lower_wmma3x_tau", "orhr_tau_finish", "mixed_bmm"],
extra_cuda_cflags=["-O3", "--use_fast_math", "-gencode=arch=compute_100a,code=sm_100a"],
extra_ldflags=["-lcublas"], verbose=True)
_BIG = 1.0e30
_EPSF = 1.1920929e-07 # fp32 eps
# n4096 trailing in bf16-mixed cuBLAS (jb>64 path only). The final update
# (C -= V@Y) is always done bf16-mixed: V,Y -> bf16, accumulated into fp32 C in
# place (beta=1), no intermediate, C never bulk-converted. _Z_BF16 additionally
# does Z = V^T @ C in bf16 (requires one bf16 copy of C); default off to keep C
# fp32 on the read side and protect the factor-residual margin.
_Z_BF16 = False
def _eye_batch(batch, jb, device, dtype):
return torch.eye(jb, device=device, dtype=dtype).expand(batch, jb, jb).contiguous()
def _chol_upper_retry(G, I, base_shift, include_zero=True):
G = 0.5 * (G + G.transpose(1, 2))
last = None
mults = (0.0, 1.0, 8.0, 64.0, 512.0, 4096.0, 32768.0, 262144.0)
if not include_zero:
mults = mults[1:]
for mult in mults:
try:
return torch.linalg.cholesky(G + (base_shift * mult) * I, upper=True)
except Exception as e:
last = e
raise last
def _gram_cqr(X):
B, m, jb = X.shape
if X.is_cuda and X.dtype == torch.float32 and B <= 4 and jb == 128 and m >= 1024 and (m % 8) == 0:
Xc = X.contiguous()
G = torch.empty((B, 128, 128), device=X.device, dtype=X.dtype)
splitK = 8 if m >= 2048 else 4
P = torch.empty((B, splitK, 128, 128), device=X.device, dtype=X.dtype)
mod.gram128_wmma3x_splitk(Xc, G, P, splitK)
return G
return X.transpose(1, 2) @ X
def _gram_cqr_equilibrated(X):
B, m, jb = X.shape
if X.is_cuda and X.dtype == torch.float32 and B <= 4 and jb == 128 and m >= 1024 and (m % 8) == 0:
Xc = X.contiguous()
G = torch.empty((B, 128, 128), device=X.device, dtype=X.dtype)
cn = torch.empty((B, 128), device=X.device, dtype=X.dtype)
splitK = 8 if m >= 2048 else 4
P = torch.empty((B, splitK, 128, 128), device=X.device, dtype=X.dtype)
mod.gram128_wmma3x_splitk_equil(Xc, G, P, cn, splitK)
return G, cn.view(B, 1, 128), Xc
cn = X.norm(dim=1, keepdim=True).clamp_min(1e-30)
Xe = X / cn
return _gram_cqr(Xe), cn, X.contiguous()
def _cqr2_shifted(X, shift_c=11.0, passes=2):
# CholeskyQR3-shifted on an equilibrated panel X (B,m,jb) -> Q orthonormal, R (true).
prev_tf32 = torch.backends.cuda.matmul.allow_tf32
torch.backends.cuda.matmul.allow_tf32 = False
try:
B, m, jb = X.shape
I = _eye_batch(B, jb, X.device, X.dtype)
G, cn, Xsolve = _gram_cqr_equilibrated(X)
diagmax = G.diagonal(dim1=1, dim2=2).amax(-1).clamp_min(1e-30).view(B, 1, 1)
s = shift_c * (m * jb + jb * (jb + 1)) * _EPSF * diagmax
R = _chol_upper_retry(G, I, s, include_zero=False)
R = R * cn
Q = torch.linalg.solve_triangular(R, Xsolve, upper=True, left=False)
for _ in range(passes - 1):
G2 = _gram_cqr(Q)
diag2 = G2.diagonal(dim1=1, dim2=2).amax(-1).clamp_min(1e-30).view(B, 1, 1)
R2 = _chol_upper_retry(G2, I, 16.0 * _EPSF * diag2)
Q = torch.linalg.solve_triangular(R2, Q, upper=True, left=False)
R = R2 @ R
return Q, R
finally:
torch.backends.cuda.matmul.allow_tf32 = prev_tf32
def _orhr_col(Q, R):
# Householder reconstruction (Ballard/ORHR_COL), batched. Q (B,m,jb) orthonormal, R (B,jb,jb).
B, m, jb = Q.shape
Q = Q.contiguous()
R = R.contiguous()
L = torch.empty(B, jb, jb, device=Q.device, dtype=Q.dtype)
Uinv = torch.empty(B, jb, jb, device=Q.device, dtype=Q.dtype)
mod.orhr_lu_signed(Q, R, L, Uinv)
H = torch.empty_like(Q)
tau = torch.empty(B, jb, device=Q.device, dtype=Q.dtype)
mod.orhr_top_tau_init(H, L, R, tau)
mod.orhr_lower_wmma3x_tau(Q, Uinv, H, tau)
mod.orhr_tau_finish(tau)
return H, tau
def _cqr2_blocked_qr(A, nb):
# Blocked QR with CholeskyQR3-panel + ORHR_COL, cuBLAS tf32 trailing (research-validated path).
B, n, _ = A.shape
A = A.contiguous()
tau = torch.zeros(B, n, device=A.device, dtype=A.dtype)
k = 0
while k < n:
jb = min(nb, n - k)
X = A[:, k:, k:k + jb].contiguous()
Q, R = _cqr2_shifted(X)
H, tp = _orhr_col(Q, R)
A[:, k:, k:k + jb] = H
tau[:, k:k + jb] = tp
_trailing_update_lower_solve(A, tau, k, jb, True)
k += jb
return A, tau
def _trailing_update(A, tau, k, jb, use_tf32, end_col=None):
hi = k + jb
n = A.shape[1]
if end_col is None: end_col = n
if hi >= end_col: return
V = torch.tril(A[:, k:, k:hi], -1)
V.diagonal(dim1=1, dim2=2).fill_(1.0)
C = A[:, k:, hi:end_col]
Z = V.transpose(1, 2) @ C
if jb <= 64: # v306: trtri path (same Y=T@Z apply)
G = V.transpose(1, 2) @ V
T = torch.empty_like(G); mod.trtri(G, tau, T, k)
Y = T @ Z
else:
taup = tau[:, k:hi]
S = V.transpose(1, 2) @ V
dinv = torch.where(taup != 0, taup.reciprocal(), torch.full_like(taup, _BIG))
S.diagonal(dim1=1, dim2=2).copy_(dinv)
Y = torch.linalg.solve_triangular(S, Z.transpose(1, 2), upper=True, left=False).transpose(1, 2)
torch.baddbmm(C, V, Y, beta=1, alpha=-1, out=C)
def _trailing_update_lower_solve(A, tau, k, jb, use_tf32, end_col=None):
hi = k + jb
n = A.shape[1]
if end_col is None: end_col = n
if hi >= end_col: return
V = torch.tril(A[:, k:, k:hi], -1)
V.diagonal(dim1=1, dim2=2).fill_(1.0)
C = A[:, k:, hi:end_col]
if jb <= 64: # v306: trtri path (unchanged; n512/n1024/n2048)
Z = V.transpose(1, 2) @ C
G = V.transpose(1, 2) @ V
T = torch.empty_like(G); mod.trtri(G, tau, T, k)
Y = T @ Z
torch.baddbmm(C, V, Y, beta=1, alpha=-1, out=C)
return
# jb>64: n4096 trailing. Big GEMMs in bf16-mixed (cuBLAS, fp32 accumulate).
# Convert only the small operands V and Y to bf16; C stays fp32.
m = V.shape[1]; N = C.shape[2]
Vb = V.to(torch.bfloat16).contiguous() # small operand
if _Z_BF16:
Cb = C.to(torch.bfloat16).contiguous()
Z = torch.empty((V.shape[0], jb, N), device=A.device, dtype=torch.float32)
mod.mixed_bmm(Vb, Cb, Z, jb, N, m, 1, 0, 1.0, 0.0) # Z = V^T @ C
else:
Z = V.transpose(1, 2) @ C # fp32/tf32 (C kept fp32)
taup = tau[:, k:hi]
S = V.transpose(1, 2) @ V # fp32 (small)
dinv = torch.where(taup != 0, taup.reciprocal(), torch.full_like(taup, _BIG))
S.diagonal(dim1=1, dim2=2).copy_(dinv)
Y = torch.linalg.solve_triangular(S.transpose(1, 2), Z, upper=False) # fp32 (small)
Yb = Y.to(torch.bfloat16).contiguous() # small operand
mod.mixed_bmm(Vb, Yb, C, m, N, jb, 0, 0, -1.0, 1.0) # C -= V @ Y (in place, fp32 accum)
def _trailing_update_tgemm(A, tau, k, jb, use_tf32, end_col=None, eye=None):
hi = k + jb
n = A.shape[1]
if end_col is None: end_col = n
if hi >= end_col: return
V = torch.tril(A[:, k:, k:hi], -1)
V.diagonal(dim1=1, dim2=2).fill_(1.0)
C = A[:, k:, hi:end_col]
Z = V.transpose(1, 2) @ C
# v305: custom batched lower-tri inverse replaces solve_triangular + the dinv setup,
# but ONLY for jb<=64 (the kernel's O(jb^2) sequential forward-sub beats cuSOLVER at
# ib=64=n512 but LOSES at ib=128=n1024). Larger jb keeps solve_triangular.
if jb <= 64:
G = V.transpose(1, 2) @ V # symmetric gram (cuBLAS)
T = torch.empty_like(G)
mod.trtri(G, tau, T, k) # T = inv(tril(S)) == old solve_triangular(S^T,eye)
Y = T @ Z
else:
taup = tau[:, k:hi]
S = V.transpose(1, 2) @ V
dinv = torch.where(taup != 0, taup.reciprocal(), torch.full_like(taup, _BIG))
S.diagonal(dim1=1, dim2=2).copy_(dinv)
if eye is None:
eye = torch.eye(jb, device=A.device, dtype=A.dtype).expand(A.shape[0], jb, jb).contiguous()
T = torch.linalg.solve_triangular(S.transpose(1, 2), eye, upper=False)
Y = T @ Z
torch.baddbmm(C, V, Y, beta=1, alpha=-1, out=C)
def _blocked_qr_geqrf_panel(A, nb):
# n4096 hybrid: the 4096-row panel won't fit smem AND b2 block-starves the
# batched-panel kernel, so the in-house path can't touch n4096 -> it was dumped
# to torch.geqrf (52ms, FP32 trailing). But geqrf on a tall-skinny PANEL strip
# spreads across SMs fine (no starvation, no smem limit). So: geqrf the panels
# (FP32, exact Householder) and do the bulk trailing in tf32 (the 90%; ~16x the
# FP32 trailing geqrf uses internally). Same compact-WY trailing already proven
# accurate on n512-2048.
B, n, _ = A.shape
tau = torch.zeros((B, n), device=A.device, dtype=A.dtype)
A = A.contiguous()
k = 0
while k < n:
jb = min(nb, n - k)
h_p, tau_p = torch.geqrf(A[:, k:, k:k + jb].contiguous())
A[:, k:, k:k + jb] = h_p
tau[:, k:k + jb] = tau_p
_trailing_update_lower_solve(A, tau, k, jb, True)
k += jb
return A, tau
def _blocked_panel(A, tau, k0, nb_blk, threads, use_tf32, sub=16, use_3x=False, use_panel64_fused=False):
# recursive-blocked Householder panel (LAPACK xGEQRT style): scalar sub-panels
# of width `sub` + WY tensor-core updates between them. Moves the within-panel
# m-dimensional work from scalar BLAS-2 (~1.5% peak) to BLAS-3/TC, producing the
# SAME exact (V,tau) as the scalar nb-panel. The WY update reuses the trtri-based
# _trailing_update (TC when use_tf32).
if use_panel64_fused and nb_blk == 64 and sub == 16:
if use_3x:
mod.panel64_fused_3x(A, tau, k0)
else:
mod.panel64_fused(A, tau, k0)
return
end = k0 + nb_blk
j = k0
while j < end:
cj = min(sub, end - j)
mod.panel_factor(A, tau, j, cj, threads)
if j + cj < end:
if use_3x:
mod.wy_apply_3x(A, tau, j, cj, end - (j + cj)) # v344 FP32-accurate WY for mixed
else:
mod.wy_apply(A, tau, j, cj, end - (j + cj)) # v316 fused WY (one launch, in-kernel TC)
j += cj
def _fused_twolevel_qr(A, nb, ib, use_tf32, active_n=None, update_tail=True, use_wy=False, use_3x_panel=False, use_panel64_fused=False):
B, n, _ = A.shape
tau = torch.zeros((B, n), device=A.device, dtype=A.dtype)
A = A.contiguous()
if active_n is None:
active_n = n
threads = 256 if B <= 128 else 128 # v277: fewer threads -> more blocks/SM -> better latency hiding (B200 sweep: n512 -8.3%, n1024 -7.6%, n2048 -4.5%)
trailing_update = _trailing_update_lower_solve if n >= 2048 else _trailing_update
outer_eye = None
if n in (512, 1024) and B > 8:
outer_eye = _eye_batch(B, ib, A.device, A.dtype)
ko = 0
while ko < active_n:
cib = min(ib, active_n - ko)
hi = ko + cib
ki = ko
while ki < hi:
cnb = min(nb, hi - ki)
if use_wy and cnb > 16:
_blocked_panel(A, tau, ki, cnb, threads, use_tf32, use_3x=use_3x_panel, use_panel64_fused=use_panel64_fused)
else:
mod.panel_factor(A, tau, ki, cnb, threads)
if ki + cnb < hi:
trailing_update(A, tau, ki, cnb, use_tf32, hi)
ki += cnb
end_col = n if update_tail else active_n
if hi < end_col:
if n in (512, 1024) and cib == ib and B > 8:
_trailing_update_tgemm(A, tau, ko, cib, use_tf32, end_col, outer_eye)
else:
trailing_update(A, tau, ko, cib, use_tf32, end_col)
ko += cib
return A, tau
def _structured_plan(data):
B, n, _ = data.shape
if n == 512:
last_col_max = data[:, :, -1].abs().amax()
if bool((last_col_max == 0.0).item()):
return 384, False
if bool((last_col_max < 1.0e-5).item()):
return 256, False
if n == 1024:
tail_copy_err = (data[:, :, -1] - data[:, :, 255]).abs().amax()
if bool((tail_copy_err < 1.0e-4).item()):
return 768, False
return n, True
def custom_kernel(data: input_t) -> output_t:
n = data.shape[1]
B = data.shape[0]
prev_tf32 = torch.backends.cuda.matmul.allow_tf32
try:
if n <= 64:
torch.backends.cuda.matmul.allow_tf32 = False
B, n, _ = data.shape
tau = torch.zeros((B, n), device=data.device, dtype=data.dtype)
A = data.clone().contiguous()
if n <= 32:
mod.small_qr_warp(A, tau) # warp-per-matrix, no block syncs
else:
mod.small_qr(A, tau)
return A, tau
use_tf32 = n >= 512
if n == 512:
B = data.shape[0]
if B <= 128:
use_tf32 = False
else:
tail0 = data[:, :, 384:].abs().amax(dim=(1, 2)) == 0.0
last_tiny = data[:, :, -1].abs().amax(dim=1) < 1.0e-5
any_tail0 = bool(tail0.any().item())
all_tail0 = bool(tail0.all().item())
any_tiny = bool(last_tiny.any().item())
all_tiny = bool(last_tiny.all().item())
if (any_tail0 and not all_tail0) or (any_tiny and not all_tiny) or (all_tiny and not all_tail0):
use_tf32 = False
torch.backends.cuda.matmul.allow_tf32 = use_tf32
if n >= 4096:
B = data.shape[0]
if bool((torch.tril(data, diagonal=-1).abs().amax() == 0.0).item()):
tau = torch.zeros((B, n), device=data.device, dtype=data.dtype)
return data.clone().contiguous(), tau
torch.backends.cuda.matmul.allow_tf32 = True # tf32 trailing (gate is loose at n=4096)
return _cqr2_blocked_qr(data.clone(), 128) # v614: keep B<=2 on CholeskyQR3/CQR2, not stale geqrf
# v261 per-shape nb: after v257's conflict-free panel, the v260 padded
# re-sweep showed the nb optimum shifted up (a larger nb shrinks the now-
# prominent inner trailing, and the padded panel makes the extra nb cheap).
# Within-run best: n512->24, n1024->28, n2048->24 (n2048 capped at 24 by
# the 227KB smem budget at ld=25); n176/n352 stay 28.
_NB = {176: 32, 352: 32, 512: 32, 1024: 32, 2048: 24} # v292: n1024 28->32 (post-v277 B200 re-sweep: nb32 8.33 vs nb28 8.61, fewer-passes wins even at 1 block/SM) # v284: n176/n352 28->32
nb = _NB.get(n, 20)
active_n, update_tail = _structured_plan(data)
# v262 per-shape/precision ib (outer block width). The inner trailing is
# the #2 phase; ib sets the inner/outer work split. Local n512 sweep
# (shared 4080, relative): a SMALLER ib helps the genuinely-dense TF32
# path (less inefficient small-K inner-update; n512 dense ib=64 ~-6%), but
# ib=64 ERODES the (binding) factor-residual margin on structured/rank-
# deficient inputs -- rankdef ib=64 hit factor=14.9 vs gate 20. So ib=64
# is gated on a PURE-dense matrix (no structure detected AND TF32); every
# other n512 case uses ib=96 (safe, small win). n1024/n2048 hold at 128.
if n == 512:
# v297: n512 ib=64 universally. B200 v296 benchmark showed blanket
# structured ib=96 was stale: mixed 11.2->10.1 (-9.8%), clustered 5.81->
# 5.34 (-8.1%) at ib=64; rankdef ib=128 REGRESSED -> wants small ib too.
# accuracy-safe (rankdef ib=64 factor 15/20 ~= ib96's 14.8).
pure_dense = use_tf32 and active_n == n and update_tail
ib = 64
elif n == 2048:
ib = 48 # v271
else:
ib = min(128, n) if n >= 512 else n
# v320: fused recursive-TC panel for n512 dense/rankdef (use_tf32) AND clustered
# (use_tf32=False but active_n<n; the tf32 WY passes at factor ~12.9 < 20, a safer
# margin than rankdef's 15.3). mixed (use_tf32=False, active_n==n) stays scalar (FP32).
use_wy = (n == 512 and use_tf32)
use_wy_cl = (n == 512 and not use_tf32 and active_n < n)
use_wy_small = (n == 352) # v338: fused recursive-TC panel + tf32 on n352 dense (B200 -4.6%).
# n176 EXCLUDED: tf32 fails its tighter small-n gate on B200 (scaled 22.4>20),
# though it passes GB10 -- tf32 precision differs sm_121 vs sm_100.
# v344: n512 mixed is FP32-stuck (tf32 reflectors fail the gate) so it ran the SLOW scalar
# panel. 3xTF32 wy_apply (FP32-accurate WY on TC) lets mixed use the FUSED panel; trailing
# stays FP32 (memory-bound -> as fast as tf32, and accurate).
use_3x_panel = (n == 512 and not use_tf32 and active_n == n and update_tail and B > 128)
use_n176_3x = (n == 176) # v346: n176 is FP32-stuck (tf32 fails gate 22.4); 3xTF32 wy lets it use the fused panel
if use_wy_small:
use_tf32 = True
torch.backends.cuda.matmul.allow_tf32 = True
use_wy = True
nb = 64; ib = 64
elif use_wy or use_wy_cl:
nb = 64; ib = 64
if use_wy_cl:
torch.backends.cuda.matmul.allow_tf32 = True # enable tf32 for the clustered fused path
use_wy = True
elif use_3x_panel:
nb = 64; ib = 64
use_wy = True # fused panel, but wy_apply_3x (FP32-accurate); use_tf32 stays False -> FP32 trailing
elif use_n176_3x:
nb = 64; ib = 64
use_wy = True; use_3x_panel = True # FP32 trailing (use_tf32 False), fused 3xTF32 panel
use_panel64_fused = (
(n == 512 and B > 128) or (n == 352 and B > 8) or (n == 176)
) and active_n == n and update_tail and (use_tf32 or use_3x_panel)
H, tau = _fused_twolevel_qr(data.clone(), nb, ib, use_tf32, active_n, update_tail, use_wy=use_wy, use_3x_panel=use_3x_panel, use_panel64_fused=use_panel64_fused)
if n == 1024 and active_n == 768 and not update_tail:
H[:, :, 768:].zero_()
H[:, :256, 768:] = torch.triu(H[:, :256, :256])
return H, tau
finally:
torch.backends.cuda.matmul.allow_tf32 = prev_tf32
scrolls · 2175 lines total
Source code from GPU Mode and the KernelBot dataset · June 9 Researcher Reciprocity License v1.0
Best evidence level for this revision: reported
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