submission 70363

import torch
from torch.utils.cpp_extension import load_inline
from task import input_t, output_t

nvfp4_gemv_cuda = """
#include <cuda_fp16.h>
#include <cuda_runtime.h>

__device__ __forceinline__ float dequant_fp4_e2m1(unsigned char packed_val, int idx) {
    unsigned char fp4_bits = (idx == 0) ? (packed_val & 0x0F) : ((packed_val >> 4) & 0x0F);
    const float lut[16] = {
        0.0f, 0.5f, 1.0f, 1.5f,
        2.0f, 3.0f, 4.0f, 6.0f,
        -0.0f, -0.5f, -1.0f, -1.5f,
        -2.0f, -3.0f, -4.0f, -6.0f
    };
    return lut[fp4_bits];
}

__device__ __forceinline__ float dequant_fp8_e4m3(unsigned char fp8_bits) {
    int sign = (fp8_bits >> 7) & 0x1;
    int exp = (fp8_bits >> 3) & 0xF;
    int mant = fp8_bits & 0x7;
    
    float val;
    if (exp == 0) {
        val = ldexpf(mant / 8.0f, -6);
    } else if (exp == 15) {
        val = 448.0f;
    } else {
        val = ldexpf(1.0f + mant / 8.0f, exp - 7);
    }
    return sign ? -val : val;
}

__global__ void nvfp4_gemv_kernel(
    const unsigned char* __restrict__ a,
    const unsigned char* __restrict__ b,
    const unsigned char* __restrict__ sfa,
    const unsigned char* __restrict__ sfb,
    __half* __restrict__ c,
    int M, int K, int L, int B_rows,
    int sfa_rest_m, int sfa_rest_k, int sfb_rest_m, int sfb_rest_k,
    int64_t a_s0, int64_t a_s1, int64_t a_s2,
    int64_t b_s0, int64_t b_s1, int64_t b_s2,
    int64_t sfa_s0, int64_t sfa_s1, int64_t sfa_s2, int64_t sfa_s3, int64_t sfa_s4, int64_t sfa_s5,
    int64_t sfb_s0, int64_t sfb_s1, int64_t sfb_s2, int64_t sfb_s3, int64_t sfb_s4, int64_t sfb_s5,
    int64_t c_s0, int64_t c_s1, int64_t c_s2
) {
    extern __shared__ unsigned char smem[];
    unsigned char* b_shared = smem;
    unsigned char* sfb_shared = smem + (K / 2);
    
    const int warp_id = threadIdx.y;
    const int lane_id = threadIdx.x;
    const int m = blockIdx.x * blockDim.y + warp_id;
    const int l = blockIdx.y;
    const int tid = threadIdx.x + threadIdx.y * blockDim.x;
    
    if (m >= M || l >= L) return;
    
    const int K_bytes = K / 2;
    const int K_blocks = K / 16;
    const int b_m = 0;
    
    // Vectorized loading of b into shared memory
    // Process 4 bytes per thread for coalesced access
    constexpr int B_VEC_SIZE = 4;
    for (int byte_idx = tid * B_VEC_SIZE; byte_idx < K_bytes; byte_idx += (blockDim.x * blockDim.y) * B_VEC_SIZE) {
        if (byte_idx + B_VEC_SIZE <= K_bytes) {
            const int64_t b_offset = byte_idx * b_s1 + l * b_s2;
            *reinterpret_cast<uint32_t*>(&b_shared[byte_idx]) = 
                *reinterpret_cast<const uint32_t*>(&b[b_offset]);
        } else {
            // Handle remainder
            for (int i = 0; i < B_VEC_SIZE && byte_idx + i < K_bytes; ++i) {
                b_shared[byte_idx + i] = __ldg(&b[(byte_idx + i) * b_s1 + l * b_s2]);
            }
        }
    }
    
    // Precompute scale offset components for matrix a
    const int mm = m / 128;
    const int mm32 = m % 32;
    const int mm4 = (m % 128) / 32;
    const int64_t sfa_m_part = mm32 * sfa_s0 + mm4 * sfa_s1 + mm * sfa_s2 + l * sfa_s5;
    
    // Vectorized loading of sfb into shared memory
    const int64_t sfb_l_offset = l * sfb_s5;
    for (int idx = tid; idx < K_blocks; idx += blockDim.x * blockDim.y) {
        const int kk = idx / 4;
        const int kk4 = idx % 4;
        const int64_t sfb_offset = b_m * sfb_s0 + kk4 * sfb_s3 + kk * sfb_s4 + sfb_l_offset;
        sfb_shared[idx] = __ldg(&sfb[sfb_offset]);
    }
    __syncthreads();
    
    float thread_acc = 0.0f;
    
    // Vectorized loop: each thread processes 4 consecutive bytes per iteration
    // This maintains coalescing while allowing vectorized loads
    constexpr int VEC_SIZE = 4;
    const int total_vec_iters = K_bytes / (warpSize * VEC_SIZE);
    const int remainder_start = total_vec_iters * warpSize * VEC_SIZE;
    
    // Main vectorized loop - process VEC_SIZE bytes per thread per iteration
    for (int iter = 0; iter < total_vec_iters; ++iter) {
        const int k_byte_base = iter * warpSize * VEC_SIZE + lane_id * VEC_SIZE;
        const int64_t a_offset = m * a_s0 + k_byte_base * a_s1 + l * a_s2;
        
        // Vectorized load: 4 bytes (8 FP4 values) per thread
        // Threads 0-31 load bytes [0-3], [4-7], [8-11], ..., [124-127] - fully coalesced
        uint32_t a_vec = *reinterpret_cast<const uint32_t*>(&a[a_offset]);
        unsigned char a_bytes[4];
        *reinterpret_cast<uint32_t*>(a_bytes) = a_vec;
        
        // Process 4 consecutive bytes
        #pragma unroll
        for (int i = 0; i < VEC_SIZE; ++i) {
            const int k_byte = k_byte_base + i;
            const int k = k_byte * 2;
            const int k_block = k_byte >> 3;
            
            const unsigned char a_val = a_bytes[i];
            const float a_fp4_0 = dequant_fp4_e2m1(a_val, 0);
            const float a_fp4_1 = dequant_fp4_e2m1(a_val, 1);
            
            const unsigned char b_val = b_shared[k_byte];
            const float b_fp4_0 = dequant_fp4_e2m1(b_val, 0);
            const float b_fp4_1 = dequant_fp4_e2m1(b_val, 1);
            
            const int kk = k_block / 4;
            const int kk4 = k_block % 4;
            const int64_t sfa_offset = sfa_m_part + kk4 * sfa_s3 + kk * sfa_s4;
            
            if (sfa_offset >= 0) {
                const float scale_a = dequant_fp8_e4m3(__ldg(&sfa[sfa_offset]));
                const float scale_b = dequant_fp8_e4m3(sfb_shared[k_block]);
                
                const float a_scaled_0 = a_fp4_0 * scale_a;
                const float a_scaled_1 = a_fp4_1 * scale_a;
                const float b_scaled_0 = b_fp4_0 * scale_b;
                const float b_scaled_1 = b_fp4_1 * scale_b;
                
                thread_acc += a_scaled_0 * b_scaled_0;
                thread_acc += a_scaled_1 * b_scaled_1;
            }
        }
    }
    
    // Handle remainder bytes (< warpSize * VEC_SIZE)
    for (int k_byte = remainder_start + lane_id; k_byte < K_bytes; k_byte += warpSize) {
        const int k = k_byte * 2;
        const int k_block = k_byte >> 3;
        
        const int64_t a_offset = m * a_s0 + k_byte * a_s1 + l * a_s2;
        const unsigned char a_val = __ldg(&a[a_offset]);
        
        const float a_fp4_0 = dequant_fp4_e2m1(a_val, 0);
        const float a_fp4_1 = dequant_fp4_e2m1(a_val, 1);
        
        const unsigned char b_val = b_shared[k_byte];
        const float b_fp4_0 = dequant_fp4_e2m1(b_val, 0);
        const float b_fp4_1 = dequant_fp4_e2m1(b_val, 1);
        
        const int kk = k_block / 4;
        const int kk4 = k_block % 4;
        const int64_t sfa_offset = sfa_m_part + kk4 * sfa_s3 + kk * sfa_s4;
        
        if (sfa_offset >= 0) {
            const float scale_a = dequant_fp8_e4m3(__ldg(&sfa[sfa_offset]));
            const float scale_b = dequant_fp8_e4m3(sfb_shared[k_block]);
            
            const float a_scaled_0 = a_fp4_0 * scale_a;
            const float a_scaled_1 = a_fp4_1 * scale_a;
            const float b_scaled_0 = b_fp4_0 * scale_b;
            const float b_scaled_1 = b_fp4_1 * scale_b;
            
            thread_acc += a_scaled_0 * b_scaled_0;
            thread_acc += a_scaled_1 * b_scaled_1;
        }
    }
    
    // Warp reduction
    #pragma unroll
    for (int offset = 16; offset > 0; offset >>= 1) {
        thread_acc += __shfl_down_sync(0xFFFFFFFF, thread_acc, offset);
    }
    
    if (lane_id == 0) {
        const int64_t c_offset = m * c_s0 + l * c_s2;
        c[c_offset] = __float2half(thread_acc);
    }
}

torch::Tensor nvfp4_gemv(
    torch::Tensor a,
    torch::Tensor b,
    torch::Tensor sfa_permuted,
    torch::Tensor sfb_permuted,
    torch::Tensor c
) {
    TORCH_CHECK(a.device().is_cuda(), "tensors must be CUDA");
    TORCH_CHECK(sfa_permuted.dim() == 6, "sfa_permuted must be 6D");
    TORCH_CHECK(sfb_permuted.dim() == 6, "sfb_permuted must be 6D");
    
    unsigned char* a_ptr = reinterpret_cast<unsigned char*>(a.data_ptr());
    unsigned char* b_ptr = reinterpret_cast<unsigned char*>(b.data_ptr());
    unsigned char* sfa_ptr = reinterpret_cast<unsigned char*>(sfa_permuted.data_ptr());
    unsigned char* sfb_ptr = reinterpret_cast<unsigned char*>(sfb_permuted.data_ptr());
    
    int M = a.size(0);
    int K_bytes = a.size(1);
    int L = a.size(2);
    int K = K_bytes * 2;
    int B_rows = b.size(0);
    
    int sfa_dim2 = sfa_permuted.size(2);
    int sfa_dim4 = sfa_permuted.size(4);
    int sfb_dim2 = sfb_permuted.size(2);
    int sfb_dim4 = sfb_permuted.size(4);
    
    dim3 block(32, 16);
    dim3 grid((M + 15) / 16, L);
    size_t smem_size = K_bytes + K / 16;
    
    nvfp4_gemv_kernel<<<grid, block, smem_size>>>(
        a_ptr, b_ptr, sfa_ptr, sfb_ptr,
        reinterpret_cast<__half*>(c.data_ptr<at::Half>()),
        M, K, L, B_rows,
        sfa_dim2, sfa_dim4, sfb_dim2, sfb_dim4,
        a.stride(0), a.stride(1), a.stride(2),
        b.stride(0), b.stride(1), b.stride(2),
        sfa_permuted.stride(0), sfa_permuted.stride(1), sfa_permuted.stride(2),
        sfa_permuted.stride(3), sfa_permuted.stride(4), sfa_permuted.stride(5),
        sfb_permuted.stride(0), sfb_permuted.stride(1), sfb_permuted.stride(2),
        sfb_permuted.stride(3), sfb_permuted.stride(4), sfb_permuted.stride(5),
        c.stride(0), c.stride(1), c.stride(2)
    );
    
    cudaError_t err = cudaGetLastError();
    TORCH_CHECK(err == cudaSuccess, "CUDA error: ", cudaGetErrorString(err));
    
    return c;
}
"""

nvfp4_gemv_cpp = """
#include <torch/extension.h>
torch::Tensor nvfp4_gemv(
    torch::Tensor a,
    torch::Tensor b,
    torch::Tensor sfa,
    torch::Tensor sfb,
    torch::Tensor c
);
"""

nvfp4_module = load_inline(
    name='nvfp4_gemv_vectorized',
    cpp_sources=nvfp4_gemv_cpp,
    cuda_sources=nvfp4_gemv_cuda,
    functions=['nvfp4_gemv'],
    verbose=False,
    extra_cuda_cflags=['-O3', '--use_fast_math', '-arch=sm_100']
)

def custom_kernel(data: input_t) -> output_t:
    """
    NVFP4 GEMV with vectorized memory access (4-byte loads via uint32_t)
    
    Optimization strategy:
    - Each thread loads 4 consecutive bytes per iteration (fully coalesced)
    - All 32 threads in warp remain active throughout execution
    - Maintains computational equivalence through consistent accumulation order
    - Leverages B200's 8 TB/s HBM3e bandwidth with optimized access patterns
    """
    a, b, _, _, sfa_permuted, sfb_permuted, c = data
    return nvfp4_module.nvfp4_gemv(a, b, sfa_permuted, sfb_permuted, c)