submission 189530

import torch
from torch.utils.cpp_extension import load_inline


_ext = None
_g1_cache = {}


def _get_ext():
    global _ext
    if _ext is not None:
        return _ext

    cpp_src = r"""
#include <torch/extension.h>
#include <ATen/ATen.h>

void gemm_cuda(
    const at::Tensor& a,
    const at::Tensor& b,
    const at::Tensor& sfa,
    const at::Tensor& sfb,
    at::Tensor& out);

void gemm_silu_mul_cuda(
    const at::Tensor& a,
    const at::Tensor& b,
    const at::Tensor& sfa,
    const at::Tensor& sfb,
    const at::Tensor& g1,
    at::Tensor& out,
    int64_t out_stride,
    int64_t out_offset);

torch::Tensor gemm(
    torch::Tensor a,
    torch::Tensor b,
    torch::Tensor sfa,
    torch::Tensor sfb,
    torch::Tensor out) {
    gemm_cuda(a, b, sfa, sfb, out);
    return out;
}

void gemm_silu_mul(
    torch::Tensor a,
    torch::Tensor b,
    torch::Tensor sfa,
    torch::Tensor sfb,
    torch::Tensor g1,
    torch::Tensor out,
    int64_t out_stride,
    int64_t out_offset) {
    gemm_silu_mul_cuda(a, b, sfa, sfb, g1, out, out_stride, out_offset);
}

PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("gemm", &gemm, "nvfp4 gemm");
    m.def("gemm_silu_mul", &gemm_silu_mul, "nvfp4 gemm silu mul");
}
"""

    cuda_src = r"""
#include <ATen/ATen.h>
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <cudaTypedefs.h>
#include <stdint.h>

constexpr int WARP_SIZE = 32;
constexpr int MMA_K = 64;
constexpr uint64_t EVICT_NORMAL = 0x1000000000000000;
constexpr uint64_t EVICT_FIRST = 0x12F0000000000000;
constexpr uint64_t EVICT_LAST = 0x14F0000000000000;

__device__ inline constexpr uint64_t desc_encode(uint64_t x) {
  return (x & 0x3FFFFULL) >> 4ULL;
}

__device__ uint32_t elect_sync() {
  uint32_t pred = 0;
  asm volatile(
    "{\n\t"
    ".reg .pred %%px;\n\t"
    "elect.sync _|%%px, %1;\n\t"
    "@%%px mov.s32 %0, 1;\n\t"
    "}"
    : "+r"(pred)
    : "r"(0xFFFFFFFF)
  );
  return pred;
}

__device__ inline void mbarrier_init(int mbar_addr, int count) {
  asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;" :: "r"(mbar_addr), "r"(count));
}

__device__ void mbarrier_wait(int mbar_addr, int phase) {
  uint32_t ticks = 0x989680;
  asm volatile(
    "{\n\t"
    ".reg .pred P1;\n\t"
    "LAB_WAIT:\n\t"
    "mbarrier.try_wait.parity.acquire.cta.shared::cta.b64 P1, [%0], %1, %2;\n\t"
    "@P1 bra.uni DONE;\n\t"
    "bra.uni LAB_WAIT;\n\t"
    "DONE:\n\t"
    "}"
    :: "r"(mbar_addr), "r"(phase), "r"(ticks)
  );
}

__device__ inline void tma_gmem2smem(int dst, const void *src, int size, int mbar_addr, uint64_t cache_policy) {
  asm volatile("cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.L2::cache_hint [%0], [%1], %2, [%3], %4;"
              :: "r"(dst), "l"(src), "r"(size), "r"(mbar_addr), "l"(cache_policy));
}

__device__ inline void tma_3d_gmem2smem(int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr, uint64_t cache_policy) {
  asm volatile("cp.async.bulk.tensor.3d.shared::cta.global.mbarrier::complete_tx::bytes.cta_group::1.L2::cache_hint "
              "[%0], [%1, {%2, %3, %4}], [%5], %6;"
              :: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z), "r"(mbar_addr), "l"(cache_policy)
              : "memory");
}

__device__ inline void tcgen05_cp_nvfp4(int taddr, uint64_t s_desc) {
  asm volatile("tcgen05.cp.cta_group::1.32x128b.warpx4 [%0], %1;" :: "r"(taddr), "l"(s_desc));
}

__device__ inline void tcgen05_mma_nvfp4(
  uint64_t a_desc,
  uint64_t b_desc,
  uint32_t i_desc,
  int scale_A_tmem,
  int scale_B_tmem,
  int enable_input_d
) {
  const int d_tmem = 0;
  asm volatile(
    "{\n\t"
    ".reg .pred p;\n\t"
    "setp.ne.b32 p, %6, 0;\n\t"
    "tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16 [%0], %1, %2, %3, [%4], [%5], p;\n\t"
    "}"
    :: "r"(d_tmem), "l"(a_desc), "l"(b_desc), "r"(i_desc),
       "r"(scale_A_tmem), "r"(scale_B_tmem), "r"(enable_input_d)
  );
}

struct SHAPE {
  static constexpr char _16x256b[] = ".16x256b";
};

struct NUM {
  static constexpr char x4[] = ".x4";
  static constexpr char x8[] = ".x8";
  static constexpr char x16[] = ".x16";
};

template <const char *SHAPE, const char *NUM>
__device__ inline void tcgen05_ld_16regs(float *tmp, int row, int col) {
  asm volatile("tcgen05.ld.sync.aligned%17%18.b32 "
              "{ %0,  %1,  %2,  %3,  %4,  %5,  %6,  %7, "
              "  %8,  %9, %10, %11, %12, %13, %14, %15}, [%16];"
              : "=f"(tmp[ 0]), "=f"(tmp[ 1]), "=f"(tmp[ 2]), "=f"(tmp[ 3]), "=f"(tmp[ 4]), "=f"(tmp[ 5]), "=f"(tmp[ 6]), "=f"(tmp[ 7]),
                "=f"(tmp[ 8]), "=f"(tmp[ 9]), "=f"(tmp[10]), "=f"(tmp[11]), "=f"(tmp[12]), "=f"(tmp[13]), "=f"(tmp[14]), "=f"(tmp[15])
              : "r"((row << 16) | col), "C"(SHAPE), "C"(NUM));
}

template <const char *SHAPE, const char *NUM>
__device__ inline void tcgen05_ld_32regs(float *tmp, int row, int col) {
  asm volatile("tcgen05.ld.sync.aligned%33%34.b32 "
              "{ %0,  %1,  %2,  %3,  %4,  %5,  %6,  %7, "
              "  %8,  %9, %10, %11, %12, %13, %14, %15, "
              " %16, %17, %18, %19, %20, %21, %22, %23, "
              " %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
              : "=f"(tmp[ 0]), "=f"(tmp[ 1]), "=f"(tmp[ 2]), "=f"(tmp[ 3]), "=f"(tmp[ 4]), "=f"(tmp[ 5]), "=f"(tmp[ 6]), "=f"(tmp[ 7]),
                "=f"(tmp[ 8]), "=f"(tmp[ 9]), "=f"(tmp[10]), "=f"(tmp[11]), "=f"(tmp[12]), "=f"(tmp[13]), "=f"(tmp[14]), "=f"(tmp[15]),
                "=f"(tmp[16]), "=f"(tmp[17]), "=f"(tmp[18]), "=f"(tmp[19]), "=f"(tmp[20]), "=f"(tmp[21]), "=f"(tmp[22]), "=f"(tmp[23]),
                "=f"(tmp[24]), "=f"(tmp[25]), "=f"(tmp[26]), "=f"(tmp[27]), "=f"(tmp[28]), "=f"(tmp[29]), "=f"(tmp[30]), "=f"(tmp[31])
              : "r"((row << 16) | col), "C"(SHAPE), "C"(NUM));
}

template <const char *SHAPE, const char *NUM>
__device__ inline void tcgen05_ld_64regs(float *tmp, int row, int col) {
  asm volatile("tcgen05.ld.sync.aligned%65%66.b32 "
              "{ %0,  %1,  %2,  %3,  %4,  %5,  %6,  %7, "
              "  %8,  %9, %10, %11, %12, %13, %14, %15, "
              " %16, %17, %18, %19, %20, %21, %22, %23, "
              " %24, %25, %26, %27, %28, %29, %30, %31, "
              " %32, %33, %34, %35, %36, %37, %38, %39, "
              " %40, %41, %42, %43, %44, %45, %46, %47, "
              " %48, %49, %50, %51, %52, %53, %54, %55, "
              " %56, %57, %58, %59, %60, %61, %62, %63}, [%64];"
              : "=f"(tmp[ 0]), "=f"(tmp[ 1]), "=f"(tmp[ 2]), "=f"(tmp[ 3]), "=f"(tmp[ 4]), "=f"(tmp[ 5]), "=f"(tmp[ 6]), "=f"(tmp[ 7]),
                "=f"(tmp[ 8]), "=f"(tmp[ 9]), "=f"(tmp[10]), "=f"(tmp[11]), "=f"(tmp[12]), "=f"(tmp[13]), "=f"(tmp[14]), "=f"(tmp[15]),
                "=f"(tmp[16]), "=f"(tmp[17]), "=f"(tmp[18]), "=f"(tmp[19]), "=f"(tmp[20]), "=f"(tmp[21]), "=f"(tmp[22]), "=f"(tmp[23]),
                "=f"(tmp[24]), "=f"(tmp[25]), "=f"(tmp[26]), "=f"(tmp[27]), "=f"(tmp[28]), "=f"(tmp[29]), "=f"(tmp[30]), "=f"(tmp[31]),
                "=f"(tmp[32]), "=f"(tmp[33]), "=f"(tmp[34]), "=f"(tmp[35]), "=f"(tmp[36]), "=f"(tmp[37]), "=f"(tmp[38]), "=f"(tmp[39]),
                "=f"(tmp[40]), "=f"(tmp[41]), "=f"(tmp[42]), "=f"(tmp[43]), "=f"(tmp[44]), "=f"(tmp[45]), "=f"(tmp[46]), "=f"(tmp[47]),
                "=f"(tmp[48]), "=f"(tmp[49]), "=f"(tmp[50]), "=f"(tmp[51]), "=f"(tmp[52]), "=f"(tmp[53]), "=f"(tmp[54]), "=f"(tmp[55]),
                "=f"(tmp[56]), "=f"(tmp[57]), "=f"(tmp[58]), "=f"(tmp[59]), "=f"(tmp[60]), "=f"(tmp[61]), "=f"(tmp[62]), "=f"(tmp[63])
              : "r"((row << 16) | col), "C"(SHAPE), "C"(NUM));
}

__device__ inline void tcgen05_ld_16x256bx4(float *tmp, int row, int col) { tcgen05_ld_16regs<SHAPE::_16x256b, NUM::x4>(tmp, row, col); }
__device__ inline void tcgen05_ld_16x256bx8(float *tmp, int row, int col) { tcgen05_ld_32regs<SHAPE::_16x256b, NUM::x8>(tmp, row, col); }
__device__ inline void tcgen05_ld_16x256bx16(float *tmp, int row, int col) { tcgen05_ld_64regs<SHAPE::_16x256b, NUM::x16>(tmp, row, col); }

void check_cu(CUresult err) {
  if (err == CUDA_SUCCESS) return;
  const char *error_msg_ptr;
  if (cuGetErrorString(err, &error_msg_ptr) != CUDA_SUCCESS)
    error_msg_ptr = "cuTensorMapEncodeTiled error";
  TORCH_CHECK(false, error_msg_ptr);
}

void check_cuda(cudaError_t err) {
  if (err == cudaSuccess) return;
  TORCH_CHECK(false, cudaGetErrorString(err));
}

void init_AB_tmap(
  CUtensorMap *tmap,
  const char *ptr,
  uint64_t global_height, uint64_t global_width,
  uint32_t shared_height, uint32_t shared_width
) {
  constexpr uint32_t rank = 3;
  uint64_t globalDim[rank]       = {256, global_height, global_width / 256};
  uint64_t globalStrides[rank-1] = {global_width / 2, 128};
  uint32_t boxDim[rank]          = {256, shared_height, shared_width / 256};
  uint32_t elementStrides[rank]  = {1, 1, 1};

  auto err = cuTensorMapEncodeTiled(
    tmap,
    CUtensorMapDataType::CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN8B,
    rank,
    (void *)ptr,
    globalDim,
    globalStrides,
    boxDim,
    elementStrides,
    CUtensorMapInterleave::CU_TENSOR_MAP_INTERLEAVE_NONE,
    CUtensorMapSwizzle::CU_TENSOR_MAP_SWIZZLE_128B,
    CUtensorMapL2promotion::CU_TENSOR_MAP_L2_PROMOTION_NONE,
    CUtensorMapFloatOOBfill::CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE
  );
  check_cu(err);
}

template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES, bool FUSE>
__global__ __launch_bounds__(BLOCK_M + 2 * WARP_SIZE)
void kernel(
  const __grid_constant__ CUtensorMap A_tmap,
  const __grid_constant__ CUtensorMap B_tmap,
  const char *__restrict__ SFA_ptr,
  const char *__restrict__ SFB_ptr,
  const half *__restrict__ g1_ptr,
  half *__restrict__ C_ptr,
  int M, int N,
  int64_t out_stride,
  int64_t out_offset
) {
  const int tid = threadIdx.x;
  const int bid = blockIdx.y;

  const int lane_id = tid % WARP_SIZE;
  const int warp_id = tid / WARP_SIZE;

  const int grid_m = M / BLOCK_M;
  const int grid_n = N / BLOCK_N;
  const int bid_m = bid / grid_n;
  const int bid_n = bid % grid_n;

  const int off_m = bid_m * BLOCK_M;
  const int off_n = bid_n * BLOCK_N;

  constexpr int NUM_WARPS = BLOCK_M / WARP_SIZE + 2;

  extern __shared__ __align__(1024) char smem_ptr[];
  const int smem = static_cast<int>(__cvta_generic_to_shared(smem_ptr));
  constexpr int A_size = BLOCK_M * BLOCK_K / 2;
  constexpr int B_size = BLOCK_N * BLOCK_K / 2;
  constexpr int SFA_size = 128 * BLOCK_K / 16;
  constexpr int SFB_size = 128 * BLOCK_K / 16;
  constexpr int STAGE_SIZE = A_size + B_size + SFA_size + SFB_size;

  #pragma nv_diag_suppress static_var_with_dynamic_init
  __shared__ int64_t mbars[NUM_STAGES * 2 + 1];
  const int tma_mbar_addr = static_cast<int>(__cvta_generic_to_shared(mbars));
  const int mma_mbar_addr = tma_mbar_addr + NUM_STAGES * 8;
  const int mainloop_mbar_addr = mma_mbar_addr + NUM_STAGES * 8;

  constexpr int SFA_tmem = BLOCK_N;
  constexpr int SFB_tmem = SFA_tmem + 4 * (BLOCK_K / MMA_K);

  if (warp_id == 0 && elect_sync()) {
    for (int i = 0; i < NUM_STAGES * 2 + 1; i++)
      mbarrier_init(tma_mbar_addr + i * 8, 1);
    asm volatile("fence.mbarrier_init.release.cluster;");
  } else if (warp_id == 1) {
    asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(smem), "r"(BLOCK_N * 2));
  }
  __syncthreads();

  constexpr int num_iters = K / BLOCK_K;

  if (warp_id == NUM_WARPS - 2 && elect_sync()) {
    uint64_t cache_A = EVICT_NORMAL;
    uint64_t cache_B = EVICT_FIRST;

    auto issue_tma = [&](int iter_k, int stage_id) {
      const int mbar_addr = tma_mbar_addr + stage_id * 8;
      const int A_smem = smem + stage_id * STAGE_SIZE;
      const int B_smem = A_smem + A_size;
      const int SFA_smem = B_smem + B_size;
      const int SFB_smem = SFA_smem + SFA_size;

      const int off_k = iter_k * BLOCK_K;
      tma_3d_gmem2smem(A_smem, &A_tmap, 0, off_m, off_k / 256, mbar_addr, cache_A);
      tma_3d_gmem2smem(B_smem, &B_tmap, 0, off_n, off_k / 256, mbar_addr, cache_B);

      const int rest_k = K / 16 / 4;
      const char *SFA_src = SFA_ptr + ((off_m / 128) * rest_k + off_k / (16 * 4)) * 512;
      const char *SFB_src = SFB_ptr + ((off_n / 128) * rest_k + off_k / (16 * 4)) * 512;
      tma_gmem2smem(SFA_smem, SFA_src, SFA_size, mbar_addr, cache_A);
      tma_gmem2smem(SFB_smem, SFB_src, SFB_size, mbar_addr, cache_B);

      asm volatile("mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
                  :: "r"(mbar_addr), "r"(STAGE_SIZE) : "memory");
    };

    for (int iter_k = 0; iter_k < NUM_STAGES; iter_k++)
      issue_tma(iter_k, iter_k);

    for (int iter_k = NUM_STAGES; iter_k < num_iters; iter_k++) {
      const int stage_id = iter_k % NUM_STAGES;
      const int mma_phase = (iter_k / NUM_STAGES - 1) % 2;
      mbarrier_wait(mma_mbar_addr + stage_id * 8, mma_phase);
      issue_tma(iter_k, stage_id);
    }
  } else if (warp_id == NUM_WARPS - 1 && elect_sync()) {
    constexpr uint32_t i_desc = (1U << 7U)
                              | (1U << 10U)
                              | ((uint32_t)BLOCK_N >> 3U << 17U)
                              | ((uint32_t)128 >> 7U << 27U);

    for (int iter_k = 0; iter_k < num_iters; iter_k++) {
      const int stage_id = iter_k % NUM_STAGES;
      const int tma_phase = (iter_k / NUM_STAGES) % 2;
      mbarrier_wait(tma_mbar_addr + stage_id * 8, tma_phase);

      const int A_smem = smem + stage_id * STAGE_SIZE;
      const int B_smem = A_smem + A_size;
      const int SFA_smem = B_smem + B_size;
      const int SFB_smem = SFA_smem + SFA_size;

      auto make_desc_AB = [](int addr) -> uint64_t {
        const int SBO = 8 * 128;
        return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL) | (2ULL << 61ULL);
      };
      auto make_desc_SF = [](int addr) -> uint64_t {
        const int SBO = 8 * 16;
        return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL);
      };

      constexpr uint64_t SF_desc = make_desc_SF(0);
      const uint64_t SFA_desc = SF_desc + ((uint64_t)SFA_smem >> 4ULL);
      const uint64_t SFB_desc = SF_desc + ((uint64_t)SFB_smem >> 4ULL);

      for (int k = 0; k < BLOCK_K / MMA_K; k++) {
        uint64_t sfa_desc = SFA_desc + (uint64_t)k * (512ULL >> 4ULL);
        uint64_t sfb_desc = SFB_desc + (uint64_t)k * (512ULL >> 4ULL);
        tcgen05_cp_nvfp4(SFA_tmem + k * 4, sfa_desc);
        tcgen05_cp_nvfp4(SFB_tmem + k * 4, sfb_desc);
      }

      for (int k1 = 0; k1 < BLOCK_K / 256; k1++)
        for (int k2 = 0; k2 < 256 / MMA_K; k2++) {
          uint64_t a_desc = make_desc_AB(A_smem + k1 * BLOCK_M * 128 + k2 * 32);
          uint64_t b_desc = make_desc_AB(B_smem + k1 * BLOCK_N * 128 + k2 * 32);

          int k_sf = k1 * 4 + k2;
          const int scale_A_tmem = SFA_tmem + k_sf * 4 + (bid_m % (128 / BLOCK_M)) * (BLOCK_M / 32);
          const int scale_B_tmem = SFB_tmem + k_sf * 4 + (bid_n % (128 / BLOCK_N)) * (BLOCK_N / 32);

          const int enable_input_d = (k1 == 0 && k2 == 0) ? iter_k : 1;
          tcgen05_mma_nvfp4(a_desc, b_desc, i_desc, scale_A_tmem, scale_B_tmem, enable_input_d);
        }

      asm volatile("tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"
                  :: "r"(mma_mbar_addr + stage_id * 8) : "memory");
    }

    asm volatile("tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"
                :: "r"(mainloop_mbar_addr) : "memory");
  } else if (tid < BLOCK_M) {
    mbarrier_wait(mainloop_mbar_addr, 0);
    asm volatile("tcgen05.fence::after_thread_sync;");

    for (int m = 0; m < 32 / 16; m++) {
      float tmp[BLOCK_N / 2];
      if constexpr (BLOCK_N == 128) tcgen05_ld_16x256bx16(tmp, warp_id * 32 + m * 16, 0);
      if constexpr (BLOCK_N == 64) tcgen05_ld_16x256bx8(tmp, warp_id * 32 + m * 16, 0);
      if constexpr (BLOCK_N == 32) tcgen05_ld_16x256bx4(tmp, warp_id * 32 + m * 16, 0);
      asm volatile("tcgen05.wait::ld.sync.aligned;");

      for (int i = 0; i < BLOCK_N / 8; i++) {
        const int row = off_m + warp_id * 32 + m * 16 + lane_id / 4;
        const int col = off_n + i * 8 + (lane_id % 4) * 2;

        if constexpr (FUSE) {
          const half2 g1_row0 = reinterpret_cast<const half2 *>(g1_ptr + (row + 0) * N + col)[0];
          const half2 g1_row1 = reinterpret_cast<const half2 *>(g1_ptr + (row + 8) * N + col)[0];
          const float2 g1f0 = __half22float2(g1_row0);
          const float2 g1f1 = __half22float2(g1_row1);

          const float s0 = g1f0.x / (1.0f + __expf(-g1f0.x));
          const float s1 = g1f0.y / (1.0f + __expf(-g1f0.y));
          const float s2 = g1f1.x / (1.0f + __expf(-g1f1.x));
          const float s3 = g1f1.y / (1.0f + __expf(-g1f1.y));

          const half2 out0 = __floats2half2_rn(s0 * tmp[i * 4 + 0], s1 * tmp[i * 4 + 1]);
          const half2 out1 = __floats2half2_rn(s2 * tmp[i * 4 + 2], s3 * tmp[i * 4 + 3]);
          const int64_t out_base0 = (static_cast<int64_t>(row + 0) * N + col) * out_stride + out_offset;
          const int64_t out_base1 = (static_cast<int64_t>(row + 8) * N + col) * out_stride + out_offset;
          reinterpret_cast<half2 *>(C_ptr + out_base0)[0] = out0;
          reinterpret_cast<half2 *>(C_ptr + out_base1)[0] = out1;
        } else {
          reinterpret_cast<half2 *>(C_ptr + (row + 0) * N + col)[0] =
              __float22half2_rn({tmp[i * 4 + 0], tmp[i * 4 + 1]});
          reinterpret_cast<half2 *>(C_ptr + (row + 8) * N + col)[0] =
              __float22half2_rn({tmp[i * 4 + 2], tmp[i * 4 + 3]});
        }
      }
    }

    asm volatile("bar.sync 1, %0;" :: "r"(BLOCK_M) : "memory");
    if (warp_id == 0)
      asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(0), "r"(BLOCK_N * 2));
  }
}

template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES, bool FUSE>
void gemm_launch_impl(
  const at::Tensor& A,
  const at::Tensor& B,
  const at::Tensor& SFA,
  const at::Tensor& SFB,
  const at::Tensor& G1,
  at::Tensor& C,
  int64_t out_stride,
  int64_t out_offset
) {
  static_assert(BLOCK_K % 256 == 0);

  const int M = A.size(0);
  const int N = B.size(0);

  auto A_ptr   = reinterpret_cast<const char *>(A.data_ptr());
  auto B_ptr   = reinterpret_cast<const char *>(B.data_ptr());
  auto SFA_ptr = reinterpret_cast<const char *>(SFA.data_ptr());
  auto SFB_ptr = reinterpret_cast<const char *>(SFB.data_ptr());
  auto C_ptr   = reinterpret_cast<half *>(C.data_ptr());
  const half *g1_ptr = nullptr;
  if constexpr (FUSE) {
    g1_ptr = reinterpret_cast<const half *>(G1.data_ptr());
  }

  CUtensorMap A_tmap, B_tmap;
  init_AB_tmap(&A_tmap, A_ptr, M, K, BLOCK_M, BLOCK_K);
  init_AB_tmap(&B_tmap, B_ptr, N, K, BLOCK_N, BLOCK_K);

  dim3 grid(1, (M / BLOCK_M) * (N / BLOCK_N));
  int tb_size = BLOCK_M + 2 * WARP_SIZE;
  int AB_size = (BLOCK_M + BLOCK_N) * (BLOCK_K / 2);
  int SFAB_size = 128 * (BLOCK_K / 16) * 2;
  int smem_size = (AB_size + SFAB_size) * NUM_STAGES;

  auto this_kernel = kernel<K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES, FUSE>;
  if (smem_size > 48000)
    cudaFuncSetAttribute(this_kernel, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size);
  this_kernel<<<grid, tb_size, smem_size>>>(
      A_tmap, B_tmap, SFA_ptr, SFB_ptr, g1_ptr, C_ptr, M, N, out_stride, out_offset);
}

template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>
void gemm_launch(
  const at::Tensor& A,
  const at::Tensor& B,
  const at::Tensor& SFA,
  const at::Tensor& SFB,
  at::Tensor& C
) {
  at::Tensor dummy;
  gemm_launch_impl<K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES, false>(A, B, SFA, SFB, dummy, C, 0, 0);
}

template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>
void gemm_launch_silu_mul(
  const at::Tensor& A,
  const at::Tensor& B,
  const at::Tensor& SFA,
  const at::Tensor& SFB,
  const at::Tensor& G1,
  at::Tensor& C,
  int64_t out_stride,
  int64_t out_offset
) {
  gemm_launch_impl<K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES, true>(
      A, B, SFA, SFB, G1, C, out_stride, out_offset);
}

void gemm_cuda(
    const at::Tensor& A,
    const at::Tensor& B,
    const at::Tensor& SFA,
    const at::Tensor& SFB,
    at::Tensor& C
) {
  const int M = A.size(0);
  const int K = A.size(1) * 2;
  const int N = B.size(0);
  const bool small_m = (M <= 256);
  const bool use_large_n_7168 = (N >= 3072);
  const bool use_large_n_4096 = (N >= 4096);
  if (false) {}
  else if (K == 7168) {
    if (use_large_n_7168) {
      if (small_m) gemm_launch<7168, 128, 64, 256, 8>(A, B, SFA, SFB, C);
      else gemm_launch<7168, 128, 128, 256, 6>(A, B, SFA, SFB, C);
    }
    else gemm_launch<7168, 128, 64, 256, 8>(A, B, SFA, SFB, C);
  }
  else if (K == 4096) {
    if (use_large_n_4096) {
      if (small_m) gemm_launch<4096, 128, 64, 256, 6>(A, B, SFA, SFB, C);
      else gemm_launch<4096, 128, 128, 256, 6>(A, B, SFA, SFB, C);
    }
    else gemm_launch<4096, 128, 64, 256, 6>(A, B, SFA, SFB, C);
  }
  else if (K == 3072)  gemm_launch<3072, 128, 64, 256, 6>(A, B, SFA, SFB, C);
  else if (K == 2048)  gemm_launch<2048, 128, 64, 256, 6>(A, B, SFA, SFB, C);
  else if (K == 1536)  gemm_launch<1536, 128, 64, 256, 6>(A, B, SFA, SFB, C);
  else if (K == 2304)  gemm_launch<2304, 128, 64, 256, 6>(A, B, SFA, SFB, C);
  else if (K == 512)   gemm_launch<512, 128, 64, 256, 6>(A, B, SFA, SFB, C);
  else if (K == 256)   gemm_launch<256, 128, 64, 256, 6>(A, B, SFA, SFB, C);
  else if (K == 16384) gemm_launch<16384, 128, 64, 256, 8>(A, B, SFA, SFB, C);
  else TORCH_CHECK(false, "unsupported K");
}

void gemm_silu_mul_cuda(
    const at::Tensor& A,
    const at::Tensor& B,
    const at::Tensor& SFA,
    const at::Tensor& SFB,
    const at::Tensor& G1,
    at::Tensor& C,
    int64_t out_stride,
    int64_t out_offset
) {
  const int M = A.size(0);
  const int K = A.size(1) * 2;
  const int N = B.size(0);
  const bool small_m = (M <= 256);
  const bool use_large_n_7168 = (N >= 3072);
  const bool use_large_n_4096 = (N >= 4096);
  if (false) {}
  else if (K == 7168) {
    if (use_large_n_7168) {
      if (small_m) gemm_launch_silu_mul<7168, 128, 64, 256, 8>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
      else gemm_launch_silu_mul<7168, 128, 128, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
    }
    else gemm_launch_silu_mul<7168, 128, 64, 256, 8>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
  }
  else if (K == 4096) {
    if (use_large_n_4096) {
      if (small_m) gemm_launch_silu_mul<4096, 128, 64, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
      else gemm_launch_silu_mul<4096, 128, 128, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
    }
    else gemm_launch_silu_mul<4096, 128, 64, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
  }
  else if (K == 3072)  gemm_launch_silu_mul<3072, 128, 64, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
  else if (K == 2048)  gemm_launch_silu_mul<2048, 128, 64, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
  else if (K == 1536)  gemm_launch_silu_mul<1536, 128, 64, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
  else if (K == 2304)  gemm_launch_silu_mul<2304, 128, 64, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
  else if (K == 512)   gemm_launch_silu_mul<512, 128, 64, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
  else if (K == 256)   gemm_launch_silu_mul<256, 128, 64, 256, 6>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
  else if (K == 16384) gemm_launch_silu_mul<16384, 128, 64, 256, 8>(A, B, SFA, SFB, G1, C, out_stride, out_offset);
  else TORCH_CHECK(false, "unsupported K");
}
"""

    _ext = load_inline(
        name="nvfp4_dual_gemm_ext",
        cpp_sources=cpp_src,
        cuda_sources=cuda_src,
        functions=None,
        with_cuda=True,
        extra_cflags=["-O3", "-std=c++17"],
        extra_cuda_cflags=[
            "-O3",
            "--use_fast_math",
            "--expt-relaxed-constexpr",
            "-gencode=arch=compute_100a,code=sm_100a",
        ],
        extra_ldflags=["-lcuda"],
        verbose=False,
        no_implicit_headers=True,
    )
    return _ext


def _permute_scale(sf):
    return sf.permute(2, 4, 0, 1, 3, 5)


def _permute_scale_batch(sf):
    return sf.permute(5, 2, 4, 0, 1, 3)


def _get_g1_buffer(device, m, n):
    key = (str(device), m, n)
    buf = _g1_cache.get(key)
    if buf is None or buf.shape != (m, n) or buf.device != device:
        buf = torch.empty((m, n), device=device, dtype=torch.float16)
        _g1_cache[key] = buf
    return buf


def custom_kernel(data):
    a, b1, b2, _, _, _, sfa_p, sfb1_p, sfb2_p, c = data
    a = a.contiguous()
    b1 = b1.contiguous()
    b2 = b2.contiguous()
    out = c if c.is_contiguous() else c.contiguous()

    m, _, l = a.shape
    n = b1.size(0)
    out_stride = out.size(2)
    ext = _get_ext()
    g1 = _get_g1_buffer(a.device, m, n)

    if l == 1:
        sfa_perm = _permute_scale(sfa_p).contiguous()
        sfb1_perm = _permute_scale(sfb1_p).contiguous()
        sfb2_perm = _permute_scale(sfb2_p).contiguous()
        a_l = a[..., 0]
        b1_l = b1[..., 0]
        b2_l = b2[..., 0]
        sfa_l = sfa_perm[..., 0]
        sfb1_l = sfb1_perm[..., 0]
        sfb2_l = sfb2_perm[..., 0]
        ext.gemm(a_l, b1_l, sfa_l, sfb1_l, g1)
        ext.gemm_silu_mul(a_l, b2_l, sfa_l, sfb2_l, g1, out, out_stride, 0)
        return out

    # L>1 时提前整理布局，避免每次切片拷贝
    a_batch = a.permute(2, 0, 1).contiguous()
    b1_batch = b1.permute(2, 0, 1).contiguous()
    b2_batch = b2.permute(2, 0, 1).contiguous()
    sfa_batch = _permute_scale_batch(sfa_p).contiguous()
    sfb1_batch = _permute_scale_batch(sfb1_p).contiguous()
    sfb2_batch = _permute_scale_batch(sfb2_p).contiguous()

    for l_idx in range(l):
        a_l = a_batch[l_idx]
        b1_l = b1_batch[l_idx]
        b2_l = b2_batch[l_idx]
        sfa_l = sfa_batch[l_idx]
        sfb1_l = sfb1_batch[l_idx]
        sfb2_l = sfb2_batch[l_idx]
        ext.gemm(a_l, b1_l, sfa_l, sfb1_l, g1)
        ext.gemm_silu_mul(a_l, b2_l, sfa_l, sfb2_l, g1, out, out_stride, l_idx)

    return out


__all__ = ["custom_kernel"]