submission 371875
hekailove · python · License unknown
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Vendorable · source mirrored · license unknownView source →
No package. Vendor the mirrored source: 728 lines, June 9 Researcher Reciprocity License v1.0.
submission.py
curl "https://kernelindex.com/api/v1/implementations/kernelbot-modal-nvfp4-dual-gemm-371875?include=source"interfacepython
Compatibility
measured onNVIDIA B200
declared hardwareNVIDIA B200
architecturessm_100
dtypesfp8_e4m3, nvfp4
Benchmark evidence
1 measurement across 1 GPU, fastest first.
Operation / workload
Hardware
Latency
Rank
Observed
Reported · How evidence levels are derived →
Source and license
sourceavailable
revision digestsha256:11fdd67926cd5ee80aa873dd89f8ce96db63ebdccb3ff9d9ca62f66ed50ca2da
license declaredunknown
license concludedunknown
authorshekailove
imported2026-08-15
Techniques
Extracted from the mirrored source by pattern, never inferred. Each row cites its line.
mbarrier
__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {shared-memory
extern __shared__ __align__(1024) char smem_ptr[];tcgen05
asm volatile("tcgen05.cp.cta_group::1.32x128b.warpx4 [%0], %1;" :: "r"(taddr), "l"(s_desc));tma
"cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.L2::cache_hint "vector-width = float2
reinterpret_cast<float2 *>(C_ptr + (row + 0) * N + col)[0] = float2{tmp[i * 4 + 0], tmp[i * 4 + 1]};Kernel source
submission.py728 lines
import torch
from torch.utils.cpp_extension import load_inline
_CUDA_SRC = r"""
#include <cuda.h>
#include <cudaTypedefs.h>
#include <cuda_fp16.h>
#include <cuda_runtime.h>
#include <torch/library.h>
#include <ATen/core/Tensor.h>
constexpr int WARP_SIZE = 32;
constexpr int MMA_K = 64;
constexpr uint64_t EVICT_FIRST = 0x12F0000000000000ULL;
constexpr uint64_t EVICT_LAST = 0x14F0000000000000ULL;
__device__ __forceinline__ constexpr uint64_t desc_encode(uint64_t x) { return (x & 0x3'FFFFULL) >> 4ULL; }
__device__ __forceinline__ uint32_t elect_sync() {
uint32_t pred = 0;
asm volatile(
"{\n\t"
".reg .pred %%px;\n\t"
"elect.sync _|%%px, %1;\n\t"
"@%%px mov.s32 %0, 1;\n\t"
"}\n\t"
: "+r"(pred)
: "r"(0xFFFFFFFF)
);
return pred;
}
__device__ __forceinline__ void mbarrier_init(int mbar_addr, int count) {
asm volatile("mbarrier.init.shared::cta.b64 [%0], %1;" :: "r"(mbar_addr), "r"(count));
}
__device__ __forceinline__ void mbarrier_wait(int mbar_addr, int phase) {
uint32_t ticks = 0x989680;
asm volatile(
"{\n\t"
".reg .pred P1;\n\t"
"LAB_WAIT:\n\t"
"mbarrier.try_wait.parity.acquire.cta.shared::cta.b64 P1, [%0], %1, %2;\n\t"
"@P1 bra.uni DONE;\n\t"
"bra.uni LAB_WAIT;\n\t"
"DONE:\n\t"
"}\n\t"
:: "r"(mbar_addr), "r"(phase), "r"(ticks)
);
}
__device__ __forceinline__ void tma_gmem2smem(int dst, const void *src, int size, int mbar_addr, uint64_t cache_policy) {
asm volatile(
"cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.L2::cache_hint "
"[%0], [%1], %2, [%3], %4;"
:: "r"(dst), "l"(src), "r"(size), "r"(mbar_addr), "l"(cache_policy)
);
}
__device__ __forceinline__ void tma_3d_gmem2smem(int dst, const void *tmap_ptr, int x, int y, int z, int mbar_addr, uint64_t cache_policy) {
asm volatile(
"cp.async.bulk.tensor.3d.shared::cta.global.mbarrier::complete_tx::bytes.cta_group::1.L2::cache_hint "
"[%0], [%1, {%2, %3, %4}], [%5], %6;"
:: "r"(dst), "l"(tmap_ptr), "r"(x), "r"(y), "r"(z), "r"(mbar_addr), "l"(cache_policy)
: "memory"
);
}
__device__ __forceinline__ void tcgen05_cp_nvfp4(int taddr, uint64_t s_desc) {
asm volatile("tcgen05.cp.cta_group::1.32x128b.warpx4 [%0], %1;" :: "r"(taddr), "l"(s_desc));
}
__device__ __forceinline__ void tcgen05_mma_nvfp4(
uint64_t a_desc,
uint64_t b_desc,
uint32_t i_desc,
int scale_A_tmem,
int scale_B_tmem,
int enable_input_d
) {
const int d_tmem = 0;
asm volatile(
"{\n\t"
".reg .pred p;\n\t"
"setp.ne.b32 p, %6, 0;\n\t"
"tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16 [%0], %1, %2, %3, [%4], [%5], p;\n\t"
"}\n\t"
:: "r"(d_tmem), "l"(a_desc), "l"(b_desc), "r"(i_desc),
"r"(scale_A_tmem), "r"(scale_B_tmem), "r"(enable_input_d)
);
}
struct SHAPE { static constexpr char _16x256b[] = ".16x256b"; };
struct NUM { static constexpr char x8[] = ".x8"; };
template <const char *SHAPE_, const char *NUM_>
__device__ __forceinline__ void tcgen05_ld_32regs(float *tmp, int row, int col) {
asm volatile(
"tcgen05.ld.sync.aligned%33%34.b32 "
"{ %0, %1, %2, %3, %4, %5, %6, %7, "
" %8, %9, %10, %11, %12, %13, %14, %15, "
" %16, %17, %18, %19, %20, %21, %22, %23, "
" %24, %25, %26, %27, %28, %29, %30, %31}, [%32];"
: "=f"(tmp[ 0]), "=f"(tmp[ 1]), "=f"(tmp[ 2]), "=f"(tmp[ 3]), "=f"(tmp[ 4]), "=f"(tmp[ 5]), "=f"(tmp[ 6]), "=f"(tmp[ 7]),
"=f"(tmp[ 8]), "=f"(tmp[ 9]), "=f"(tmp[10]), "=f"(tmp[11]), "=f"(tmp[12]), "=f"(tmp[13]), "=f"(tmp[14]), "=f"(tmp[15]),
"=f"(tmp[16]), "=f"(tmp[17]), "=f"(tmp[18]), "=f"(tmp[19]), "=f"(tmp[20]), "=f"(tmp[21]), "=f"(tmp[22]), "=f"(tmp[23]),
"=f"(tmp[24]), "=f"(tmp[25]), "=f"(tmp[26]), "=f"(tmp[27]), "=f"(tmp[28]), "=f"(tmp[29]), "=f"(tmp[30]), "=f"(tmp[31])
: "r"((row << 16) | col), "C"(SHAPE_), "C"(NUM_)
);
}
__device__ __forceinline__ void tcgen05_ld_16x256bx8(float *tmp, int row, int col) {
tcgen05_ld_32regs<SHAPE::_16x256b, NUM::x8>(tmp, row, col);
}
static inline void ck_cu(CUresult err) {
if (err == CUDA_SUCCESS) return;
const char *msg = nullptr;
if (cuGetErrorString(err, &msg) != CUDA_SUCCESS) msg = "cu err";
TORCH_CHECK(false, msg);
}
static inline void init_AB_tmap(
CUtensorMap *tmap,
const char *ptr,
uint64_t global_h, uint64_t global_w,
uint32_t shared_h, uint32_t shared_w
) {
constexpr uint32_t rank = 3;
uint64_t globalDim[rank] = {256, global_h, global_w / 256};
uint64_t globalStrides[rank-1] = {global_w / 2, 128};
uint32_t boxDim[rank] = {256, shared_h, shared_w / 256};
uint32_t elementStrides[rank] = {1, 1, 1};
auto err = cuTensorMapEncodeTiled(
tmap,
CUtensorMapDataType::CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN8B,
rank,
(void *)ptr,
globalDim,
globalStrides,
boxDim,
elementStrides,
CUtensorMapInterleave::CU_TENSOR_MAP_INTERLEAVE_NONE,
CUtensorMapSwizzle::CU_TENSOR_MAP_SWIZZLE_128B,
CUtensorMapL2promotion::CU_TENSOR_MAP_L2_PROMOTION_NONE,
CUtensorMapFloatOOBfill::CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE
);
ck_cu(err);
}
template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>
__global__ __launch_bounds__(BLOCK_M + 2 * WARP_SIZE)
void gemm_f32_kernel(
const __grid_constant__ CUtensorMap A_tmap,
const __grid_constant__ CUtensorMap B_tmap,
const char *SFA_ptr,
const char *SFB_ptr,
float *C_ptr,
int M, int N
) {
const int tid = threadIdx.x;
const int bid = blockIdx.y;
const int lane_id = tid & 31;
const int warp_id = tid >> 5;
const int grid_m = M / BLOCK_M;
const int grid_n = N / BLOCK_N;
const int bid_m = bid / grid_n;
const int bid_n = bid - bid_m * grid_n;
const int off_m = bid_m * BLOCK_M;
const int off_n = bid_n * BLOCK_N;
constexpr int NUM_WARPS = BLOCK_M / WARP_SIZE + 2;
extern __shared__ __align__(1024) char smem_ptr[];
const int smem = static_cast<int>(__cvta_generic_to_shared(smem_ptr));
constexpr int A_size = BLOCK_M * BLOCK_K / 2;
constexpr int B_size = BLOCK_N * BLOCK_K / 2;
constexpr int SFA_size = 128 * BLOCK_K / 16;
constexpr int SFB_size = 128 * BLOCK_K / 16;
constexpr int STAGE_SIZE = A_size + B_size + SFA_size + SFB_size;
#pragma nv_diag_suppress static_var_with_dynamic_init
__shared__ int64_t mbars[NUM_STAGES * 2 + 1];
const int tma_mbar_addr = static_cast<int>(__cvta_generic_to_shared(mbars));
const int mma_mbar_addr = tma_mbar_addr + NUM_STAGES * 8;
const int mainloop_mbar_addr = mma_mbar_addr + NUM_STAGES * 8;
constexpr int SFA_tmem = BLOCK_N;
constexpr int SFB_tmem = SFA_tmem + 4 * (BLOCK_K / MMA_K);
if (warp_id == 0 && elect_sync()) {
for (int i = 0; i < NUM_STAGES * 2 + 1; i++) mbarrier_init(tma_mbar_addr + i * 8, 1);
asm volatile("fence.mbarrier_init.release.cluster;");
} else if (warp_id == 1) {
asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(smem), "r"(BLOCK_N * 2));
}
__syncthreads();
constexpr int num_iters = K / BLOCK_K;
if (warp_id == NUM_WARPS - 2 && elect_sync()) {
const uint64_t cache_A = EVICT_LAST;
const uint64_t cache_B = EVICT_FIRST;
auto issue_tma = [&](int iter_k, int stage_id) {
const int mbar_addr = tma_mbar_addr + stage_id * 8;
const int A_smem = smem + stage_id * STAGE_SIZE;
const int B_smem = A_smem + A_size;
const int SFA_smem = B_smem + B_size;
const int SFB_smem = SFA_smem + SFA_size;
const int off_k = iter_k * BLOCK_K;
tma_3d_gmem2smem(A_smem, &A_tmap, 0, off_m, off_k / 256, mbar_addr, cache_A);
tma_3d_gmem2smem(B_smem, &B_tmap, 0, off_n, off_k / 256, mbar_addr, cache_B);
const int rest_k = K / 16 / 4;
const char *SFA_src = SFA_ptr + ((off_m / 128) * rest_k + off_k / (16 * 4)) * 512;
const char *SFB_src = SFB_ptr + ((off_n / 128) * rest_k + off_k / (16 * 4)) * 512;
tma_gmem2smem(SFA_smem, SFA_src, SFA_size, mbar_addr, cache_A);
tma_gmem2smem(SFB_smem, SFB_src, SFB_size, mbar_addr, cache_B);
asm volatile(
"mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
:: "r"(mbar_addr), "r"(STAGE_SIZE)
: "memory"
);
};
constexpr int PRELOAD = (num_iters < NUM_STAGES) ? num_iters : NUM_STAGES;
for (int iter_k = 0; iter_k < PRELOAD; iter_k++) issue_tma(iter_k, iter_k);
for (int iter_k = NUM_STAGES; iter_k < num_iters; iter_k++) {
const int stage_id = iter_k % NUM_STAGES;
const int mma_phase = (iter_k / NUM_STAGES - 1) & 1;
mbarrier_wait(mma_mbar_addr + stage_id * 8, mma_phase);
issue_tma(iter_k, stage_id);
}
} else if (warp_id == NUM_WARPS - 1 && elect_sync()) {
constexpr int MMA_N = BLOCK_N;
constexpr int MMA_M = 128;
constexpr uint32_t i_desc = (1U << 7U) | (1U << 10U) | ((uint32_t)MMA_N >> 3U << 17U) | ((uint32_t)MMA_M >> 7U << 27U);
for (int iter_k = 0; iter_k < num_iters; iter_k++) {
const int stage_id = iter_k % NUM_STAGES;
const int tma_phase = (iter_k / NUM_STAGES) & 1;
mbarrier_wait(tma_mbar_addr + stage_id * 8, tma_phase);
const int A_smem = smem + stage_id * STAGE_SIZE;
const int B_smem = A_smem + A_size;
const int SFA_smem = B_smem + B_size;
const int SFB_smem = SFA_smem + SFA_size;
auto make_desc_AB = [](int addr) -> uint64_t {
const int SBO = 8 * 128;
return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL) | (2ULL << 61ULL);
};
auto make_desc_SF = [](int addr) -> uint64_t {
const int SBO = 8 * 16;
return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL);
};
constexpr uint64_t SF_desc = make_desc_SF(0);
const uint64_t SFA_desc = SF_desc + ((uint64_t)SFA_smem >> 4ULL);
const uint64_t SFB_desc = SF_desc + ((uint64_t)SFB_smem >> 4ULL);
for (int k = 0; k < BLOCK_K / MMA_K; k++) {
uint64_t sfa_desc = SFA_desc + (uint64_t)k * (512ULL >> 4ULL);
uint64_t sfb_desc = SFB_desc + (uint64_t)k * (512ULL >> 4ULL);
tcgen05_cp_nvfp4(SFA_tmem + k * 4, sfa_desc);
tcgen05_cp_nvfp4(SFB_tmem + k * 4, sfb_desc);
}
for (int k1 = 0; k1 < BLOCK_K / 256; k1++)
for (int k2 = 0; k2 < 256 / MMA_K; k2++) {
uint64_t a_desc = make_desc_AB(A_smem + k1 * BLOCK_M * 128 + k2 * 32);
uint64_t b_desc = make_desc_AB(B_smem + k1 * BLOCK_N * 128 + k2 * 32);
const int k_sf = k1 * 4 + k2;
const int scale_A_tmem = SFA_tmem + k_sf * 4;
const int scale_B_tmem = SFB_tmem + k_sf * 4 + (bid_n % (128 / BLOCK_N)) * (BLOCK_N / 32);
const int enable_input_d = (k1 == 0 && k2 == 0) ? iter_k : 1;
tcgen05_mma_nvfp4(a_desc, b_desc, i_desc, scale_A_tmem, scale_B_tmem, enable_input_d);
}
asm volatile(
"tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"
:: "r"(mma_mbar_addr + stage_id * 8)
: "memory"
);
}
asm volatile(
"tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"
:: "r"(mainloop_mbar_addr)
: "memory"
);
} else if (tid < BLOCK_M) {
mbarrier_wait(mainloop_mbar_addr, 0);
asm volatile("tcgen05.fence::after_thread_sync;");
for (int mm = 0; mm < 2; mm++) {
float tmp[BLOCK_N / 2];
tcgen05_ld_16x256bx8(tmp, warp_id * 32 + mm * 16, 0);
asm volatile("tcgen05.wait::ld.sync.aligned;");
#pragma unroll
for (int i = 0; i < BLOCK_N / 8; i++) {
const int row = off_m + warp_id * 32 + mm * 16 + lane_id / 4;
const int col = off_n + i * 8 + (lane_id & 3) * 2;
reinterpret_cast<float2 *>(C_ptr + (row + 0) * N + col)[0] = float2{tmp[i * 4 + 0], tmp[i * 4 + 1]};
reinterpret_cast<float2 *>(C_ptr + (row + 8) * N + col)[0] = float2{tmp[i * 4 + 2], tmp[i * 4 + 3]};
}
}
asm volatile("bar.sync 1, %0;" :: "r"(BLOCK_M) : "memory");
if (warp_id == 0) asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(0), "r"(BLOCK_N * 2));
}
}
template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>
__global__ __launch_bounds__(BLOCK_M + 2 * WARP_SIZE)
void gemm_silu_mul_kernel(
const __grid_constant__ CUtensorMap A_tmap,
const __grid_constant__ CUtensorMap B_tmap,
const char *SFA_ptr,
const char *SFB_ptr,
const float *G1_ptr,
half *Out_ptr,
int M, int N
) {
const int tid = threadIdx.x;
const int bid = blockIdx.y;
const int lane_id = tid & 31;
const int warp_id = tid >> 5;
const int grid_m = M / BLOCK_M;
const int grid_n = N / BLOCK_N;
const int bid_m = bid / grid_n;
const int bid_n = bid - bid_m * grid_n;
const int off_m = bid_m * BLOCK_M;
const int off_n = bid_n * BLOCK_N;
constexpr int NUM_WARPS = BLOCK_M / WARP_SIZE + 2;
extern __shared__ __align__(1024) char smem_ptr[];
const int smem = static_cast<int>(__cvta_generic_to_shared(smem_ptr));
constexpr int A_size = BLOCK_M * BLOCK_K / 2;
constexpr int B_size = BLOCK_N * BLOCK_K / 2;
constexpr int SFA_size = 128 * BLOCK_K / 16;
constexpr int SFB_size = 128 * BLOCK_K / 16;
constexpr int STAGE_SIZE = A_size + B_size + SFA_size + SFB_size;
#pragma nv_diag_suppress static_var_with_dynamic_init
__shared__ int64_t mbars[NUM_STAGES * 2 + 1];
const int tma_mbar_addr = static_cast<int>(__cvta_generic_to_shared(mbars));
const int mma_mbar_addr = tma_mbar_addr + NUM_STAGES * 8;
const int mainloop_mbar_addr = mma_mbar_addr + NUM_STAGES * 8;
constexpr int SFA_tmem = BLOCK_N;
constexpr int SFB_tmem = SFA_tmem + 4 * (BLOCK_K / MMA_K);
if (warp_id == 0 && elect_sync()) {
for (int i = 0; i < NUM_STAGES * 2 + 1; i++) mbarrier_init(tma_mbar_addr + i * 8, 1);
asm volatile("fence.mbarrier_init.release.cluster;");
} else if (warp_id == 1) {
asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(smem), "r"(BLOCK_N * 2));
}
__syncthreads();
constexpr int num_iters = K / BLOCK_K;
if (warp_id == NUM_WARPS - 2 && elect_sync()) {
const uint64_t cache_A = EVICT_LAST;
const uint64_t cache_B = EVICT_FIRST;
auto issue_tma = [&](int iter_k, int stage_id) {
const int mbar_addr = tma_mbar_addr + stage_id * 8;
const int A_smem = smem + stage_id * STAGE_SIZE;
const int B_smem = A_smem + A_size;
const int SFA_smem = B_smem + B_size;
const int SFB_smem = SFA_smem + SFA_size;
const int off_k = iter_k * BLOCK_K;
tma_3d_gmem2smem(A_smem, &A_tmap, 0, off_m, off_k / 256, mbar_addr, cache_A);
tma_3d_gmem2smem(B_smem, &B_tmap, 0, off_n, off_k / 256, mbar_addr, cache_B);
const int rest_k = K / 16 / 4;
const char *SFA_src = SFA_ptr + ((off_m / 128) * rest_k + off_k / (16 * 4)) * 512;
const char *SFB_src = SFB_ptr + ((off_n / 128) * rest_k + off_k / (16 * 4)) * 512;
tma_gmem2smem(SFA_smem, SFA_src, SFA_size, mbar_addr, cache_A);
tma_gmem2smem(SFB_smem, SFB_src, SFB_size, mbar_addr, cache_B);
asm volatile(
"mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"
:: "r"(mbar_addr), "r"(STAGE_SIZE)
: "memory"
);
};
constexpr int PRELOAD = (num_iters < NUM_STAGES) ? num_iters : NUM_STAGES;
for (int iter_k = 0; iter_k < PRELOAD; iter_k++) issue_tma(iter_k, iter_k);
for (int iter_k = NUM_STAGES; iter_k < num_iters; iter_k++) {
const int stage_id = iter_k % NUM_STAGES;
const int mma_phase = (iter_k / NUM_STAGES - 1) & 1;
mbarrier_wait(mma_mbar_addr + stage_id * 8, mma_phase);
issue_tma(iter_k, stage_id);
}
} else if (warp_id == NUM_WARPS - 1 && elect_sync()) {
constexpr int MMA_N = BLOCK_N;
constexpr int MMA_M = 128;
constexpr uint32_t i_desc = (1U << 7U) | (1U << 10U) | ((uint32_t)MMA_N >> 3U << 17U) | ((uint32_t)MMA_M >> 7U << 27U);
for (int iter_k = 0; iter_k < num_iters; iter_k++) {
const int stage_id = iter_k % NUM_STAGES;
const int tma_phase = (iter_k / NUM_STAGES) & 1;
mbarrier_wait(tma_mbar_addr + stage_id * 8, tma_phase);
const int A_smem = smem + stage_id * STAGE_SIZE;
const int B_smem = A_smem + A_size;
const int SFA_smem = B_smem + B_size;
const int SFB_smem = SFA_smem + SFA_size;
auto make_desc_AB = [](int addr) -> uint64_t {
const int SBO = 8 * 128;
return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL) | (2ULL << 61ULL);
};
auto make_desc_SF = [](int addr) -> uint64_t {
const int SBO = 8 * 16;
return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL);
};
constexpr uint64_t SF_desc = make_desc_SF(0);
const uint64_t SFA_desc = SF_desc + ((uint64_t)SFA_smem >> 4ULL);
const uint64_t SFB_desc = SF_desc + ((uint64_t)SFB_smem >> 4ULL);
for (int k = 0; k < BLOCK_K / MMA_K; k++) {
uint64_t sfa_desc = SFA_desc + (uint64_t)k * (512ULL >> 4ULL);
uint64_t sfb_desc = SFB_desc + (uint64_t)k * (512ULL >> 4ULL);
tcgen05_cp_nvfp4(SFA_tmem + k * 4, sfa_desc);
tcgen05_cp_nvfp4(SFB_tmem + k * 4, sfb_desc);
}
for (int k1 = 0; k1 < BLOCK_K / 256; k1++)
for (int k2 = 0; k2 < 256 / MMA_K; k2++) {
uint64_t a_desc = make_desc_AB(A_smem + k1 * BLOCK_M * 128 + k2 * 32);
uint64_t b_desc = make_desc_AB(B_smem + k1 * BLOCK_N * 128 + k2 * 32);
const int k_sf = k1 * 4 + k2;
const int scale_A_tmem = SFA_tmem + k_sf * 4;
const int scale_B_tmem = SFB_tmem + k_sf * 4 + (bid_n % (128 / BLOCK_N)) * (BLOCK_N / 32);
const int enable_input_d = (k1 == 0 && k2 == 0) ? iter_k : 1;
tcgen05_mma_nvfp4(a_desc, b_desc, i_desc, scale_A_tmem, scale_B_tmem, enable_input_d);
}
asm volatile(
"tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"
:: "r"(mma_mbar_addr + stage_id * 8)
: "memory"
);
}
asm volatile(
"tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"
:: "r"(mainloop_mbar_addr)
: "memory"
);
} else if (tid < BLOCK_M) {
mbarrier_wait(mainloop_mbar_addr, 0);
asm volatile("tcgen05.fence::after_thread_sync;");
for (int mm = 0; mm < 2; mm++) {
float tmp[BLOCK_N / 2];
tcgen05_ld_16x256bx8(tmp, warp_id * 32 + mm * 16, 0);
asm volatile("tcgen05.wait::ld.sync.aligned;");
#pragma unroll
for (int i = 0; i < BLOCK_N / 8; i++) {
const int row = off_m + warp_id * 32 + mm * 16 + lane_id / 4;
const int col = off_n + i * 8 + (lane_id & 3) * 2;
const float2 x0 = reinterpret_cast<const float2 *>(G1_ptr + (row + 0) * N + col)[0];
const float2 x8 = reinterpret_cast<const float2 *>(G1_ptr + (row + 8) * N + col)[0];
const float2 y0 = float2{tmp[i * 4 + 0], tmp[i * 4 + 1]};
const float2 y8 = float2{tmp[i * 4 + 2], tmp[i * 4 + 3]};
float2 o0;
float2 o8;
const float s00 = 1.0f / (1.0f + __expf(-x0.x));
const float s01 = 1.0f / (1.0f + __expf(-x0.y));
const float s80 = 1.0f / (1.0f + __expf(-x8.x));
const float s81 = 1.0f / (1.0f + __expf(-x8.y));
o0.x = (x0.x * s00) * y0.x;
o0.y = (x0.y * s01) * y0.y;
o8.x = (x8.x * s80) * y8.x;
o8.y = (x8.y * s81) * y8.y;
reinterpret_cast<half2 *>(Out_ptr + (row + 0) * N + col)[0] = __float22half2_rn(o0);
reinterpret_cast<half2 *>(Out_ptr + (row + 8) * N + col)[0] = __float22half2_rn(o8);
}
}
asm volatile("bar.sync 1, %0;" :: "r"(BLOCK_M) : "memory");
if (warp_id == 0) asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(0), "r"(BLOCK_N * 2));
}
}
template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>
static inline void launch_gemm_f32(
const at::Tensor& A,
const at::Tensor& B,
const at::Tensor& SFA,
const at::Tensor& SFB,
at::Tensor& C
) {
const int M = (int)A.size(0);
const int N = (int)B.size(0);
auto A_ptr = reinterpret_cast<const char *>(A.data_ptr());
auto B_ptr = reinterpret_cast<const char *>(B.data_ptr());
auto SFA_ptr = reinterpret_cast<const char *>(SFA.data_ptr());
auto SFB_ptr = reinterpret_cast<const char *>(SFB.data_ptr());
auto C_ptr = reinterpret_cast<float *>(C.data_ptr());
CUtensorMap A_tmap, B_tmap;
init_AB_tmap(&A_tmap, A_ptr, (uint64_t)M, (uint64_t)K, (uint32_t)BLOCK_M, (uint32_t)BLOCK_K);
init_AB_tmap(&B_tmap, B_ptr, (uint64_t)N, (uint64_t)K, (uint32_t)BLOCK_N, (uint32_t)BLOCK_K);
dim3 grid(1, (unsigned)((M / BLOCK_M) * (N / BLOCK_N)));
const int tb_size = BLOCK_M + 2 * WARP_SIZE;
const int AB_size = (BLOCK_M + BLOCK_N) * (BLOCK_K / 2);
const int SFAB_size = 128 * (BLOCK_K / 16) * 2;
const int smem_size = (AB_size + SFAB_size) * NUM_STAGES;
auto kptr = gemm_f32_kernel<K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES>;
if (smem_size > 48'000) cudaFuncSetAttribute(kptr, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size);
kptr<<<grid, tb_size, smem_size>>>(A_tmap, B_tmap, SFA_ptr, SFB_ptr, C_ptr, M, N);
}
template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>
static inline void launch_gemm_silu_mul(
const at::Tensor& A,
const at::Tensor& B,
const at::Tensor& SFA,
const at::Tensor& SFB,
const at::Tensor& g1,
at::Tensor& out
) {
const int M = (int)A.size(0);
const int N = (int)B.size(0);
auto A_ptr = reinterpret_cast<const char *>(A.data_ptr());
auto B_ptr = reinterpret_cast<const char *>(B.data_ptr());
auto SFA_ptr = reinterpret_cast<const char *>(SFA.data_ptr());
auto SFB_ptr = reinterpret_cast<const char *>(SFB.data_ptr());
auto G1_ptr = reinterpret_cast<const float *>(g1.data_ptr());
auto Out_ptr = reinterpret_cast<half *>(out.data_ptr());
CUtensorMap A_tmap, B_tmap;
init_AB_tmap(&A_tmap, A_ptr, (uint64_t)M, (uint64_t)K, (uint32_t)BLOCK_M, (uint32_t)BLOCK_K);
init_AB_tmap(&B_tmap, B_ptr, (uint64_t)N, (uint64_t)K, (uint32_t)BLOCK_N, (uint32_t)BLOCK_K);
dim3 grid(1, (unsigned)((M / BLOCK_M) * (N / BLOCK_N)));
const int tb_size = BLOCK_M + 2 * WARP_SIZE;
const int AB_size = (BLOCK_M + BLOCK_N) * (BLOCK_K / 2);
const int SFAB_size = 128 * (BLOCK_K / 16) * 2;
const int smem_size = (AB_size + SFAB_size) * NUM_STAGES;
auto kptr = gemm_silu_mul_kernel<K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES>;
if (smem_size > 48'000) cudaFuncSetAttribute(kptr, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size);
kptr<<<grid, tb_size, smem_size>>>(A_tmap, B_tmap, SFA_ptr, SFB_ptr, G1_ptr, Out_ptr, M, N);
}
__global__ void silu_mul_f32_vec2(const float* __restrict__ x, const float* __restrict__ y, half* __restrict__ out, int64_t n2) {
const int64_t idx = int64_t(blockIdx.x) * blockDim.x + threadIdx.x;
if (idx >= n2) return;
const float2 fx = reinterpret_cast<const float2*>(x)[idx];
const float2 fy = reinterpret_cast<const float2*>(y)[idx];
float2 o;
const float sx0 = 1.0f / (1.0f + __expf(-fx.x));
const float sx1 = 1.0f / (1.0f + __expf(-fx.y));
o.x = (fx.x * sx0) * fy.x;
o.y = (fx.y * sx1) * fy.y;
reinterpret_cast<half2*>(out)[idx] = __float22half2_rn(o);
}
static inline void launch_silu_mul_f32(const at::Tensor& g1, const at::Tensor& g2, at::Tensor& out) {
const int64_t n = out.numel();
TORCH_CHECK((n & 1) == 0, "n");
const int64_t n2 = n >> 1;
const int threads = 256;
const int blocks = (int)((n2 + threads - 1) / threads);
silu_mul_f32_vec2<<<blocks, threads>>>(
reinterpret_cast<const float*>(g1.data_ptr()),
reinterpret_cast<const float*>(g2.data_ptr()),
reinterpret_cast<half*>(out.data_ptr()),
n2
);
}
at::Tensor fused(
const at::Tensor& A,
const at::Tensor& B1,
const at::Tensor& B2,
const at::Tensor& SFA,
const at::Tensor& SFB1,
const at::Tensor& SFB2,
at::Tensor& out,
at::Tensor& g1,
at::Tensor& g2
) {
TORCH_CHECK(A.is_cuda() && B1.is_cuda() && B2.is_cuda(), "cuda");
TORCH_CHECK(SFA.is_cuda() && SFB1.is_cuda() && SFB2.is_cuda(), "cuda");
TORCH_CHECK(out.is_cuda() && g1.is_cuda() && g2.is_cuda(), "cuda");
TORCH_CHECK(A.dim() == 3 && B1.dim() == 3 && B2.dim() == 3, "dim");
TORCH_CHECK(out.dim() == 3 && g1.dim() == 3 && g2.dim() == 3, "dim");
const int64_t M = A.size(0);
const int64_t Kp = A.size(1);
const int64_t L = A.size(2);
const int64_t N = B1.size(0);
TORCH_CHECK(L == 1, "l");
TORCH_CHECK(B1.size(1) == Kp && B1.size(2) == L, "b1");
TORCH_CHECK(B2.size(1) == Kp && B2.size(2) == L, "b2");
TORCH_CHECK(out.size(0) == M && out.size(1) == N && out.size(2) == L, "out");
TORCH_CHECK(g1.size(0) == M && g1.size(1) == N && g1.size(2) == L, "g1");
TORCH_CHECK(g2.size(0) == M && g2.size(1) == N && g2.size(2) == L, "g2");
TORCH_CHECK((M % 128) == 0, "m");
TORCH_CHECK((N % 64) == 0, "n");
const int K = (int)(Kp * 2);
if (K == 7168) {
launch_gemm_f32<7168, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);
launch_gemm_silu_mul<7168, 128, 64, 256, 8>(A, B2, SFA, SFB2, g1, out);
} else if (K == 4096) {
launch_gemm_f32<4096, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);
launch_gemm_silu_mul<4096, 128, 64, 256, 8>(A, B2, SFA, SFB2, g1, out);
} else if (K == 2304) {
launch_gemm_f32<2304, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);
launch_gemm_silu_mul<2304, 128, 64, 256, 8>(A, B2, SFA, SFB2, g1, out);
} else if (K == 2048) {
launch_gemm_f32<2048, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);
launch_gemm_silu_mul<2048, 128, 64, 256, 8>(A, B2, SFA, SFB2, g1, out);
} else if (K == 1536) {
launch_gemm_f32<1536, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);
launch_gemm_silu_mul<1536, 128, 64, 256, 8>(A, B2, SFA, SFB2, g1, out);
} else if (K == 512) {
launch_gemm_f32<512, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);
launch_gemm_silu_mul<512, 128, 64, 256, 8>(A, B2, SFA, SFB2, g1, out);
} else if (K == 256) {
launch_gemm_f32<256, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);
launch_gemm_silu_mul<256, 128, 64, 256, 8>(A, B2, SFA, SFB2, g1, out);
} else {
TORCH_CHECK(false, "k ", K);
}
return out;
}
TORCH_LIBRARY(nvfp4_dual_lib, m) {
m.def("fused(Tensor A, Tensor B1, Tensor B2, Tensor SFA, Tensor SFB1, Tensor SFB2, Tensor(a!) out, Tensor(b!) g1, Tensor(c!) g2) -> Tensor");
m.impl("fused", &fused);
}
"""
_loaded = False
def _load():
global _loaded
if _loaded:
return
load_inline(
name="nvfp4_dual_ext_tc_v3",
cpp_sources="",
cuda_sources=_CUDA_SRC,
functions=None,
with_cuda=True,
extra_cuda_cflags=[
"-O3",
"-gencode=arch=compute_100a,code=sm_100a",
"--use_fast_math",
"--expt-relaxed-constexpr",
"--relocatable-device-code=false",
"-lineinfo",
],
extra_ldflags=["-lcuda"],
verbose=False,
is_python_module=False,
no_implicit_headers=True,
)
_loaded = True
_buf_cache = {}
def _get_buf(tag, shape, device):
key = (tag, shape, device)
t = _buf_cache.get(key)
if t is None or t.shape != shape or t.device != device:
t = torch.empty(shape, device=device, dtype=torch.float32)
_buf_cache[key] = t
return t
def custom_kernel(data):
_load()
a, b1, b2, _sfa, _sfb1, _sfb2, sfa_p, sfb1_p, sfb2_p, c = data
g1 = _get_buf(1, c.shape, a.device)
return torch.ops.nvfp4_dual_lib.fused(a, b1, b2, sfa_p, sfb1_p, sfb2_p, c, g1, g1)
__all__ = ["custom_kernel"]
scrolls · 728 lines total
Source code from GPU Mode and the KernelBot dataset · June 9 Researcher Reciprocity License v1.0
Changes from previous submission
Against this author's previous submission submission 255802.
- #!POPCORN leaderboard nvfp4_dual_gemm- #!POPCORN gpu NVIDIA++import torchfrom torch.utils.cpp_extension import load_inline⋯ 4 unchanged lines#include <cuda_fp16.h>#include <cuda_runtime.h>- #include <ATen/core/Tensor.h>#include <torch/library.h>+ #include <ATen/core/Tensor.h>- #include <cstdint>- #include <mutex>- #include <unordered_map>-constexpr int WARP_SIZE = 32;constexpr int MMA_K = 64;⋯ 56 unchanged linesasm volatile("tcgen05.cp.cta_group::1.32x128b.warpx4 [%0], %1;" :: "r"(taddr), "l"(s_desc));}- __device__ __forceinline__ void tcgen05_mma_nvfp4_d(- int d_tmem,+ __device__ __forceinline__ void tcgen05_mma_nvfp4(uint64_t a_desc,uint64_t b_desc,uint32_t i_desc,⋯ 1 unchanged linesint scale_B_tmem,int enable_input_d) {+ const int d_tmem = 0;asm volatile("{\n\t"".reg .pred p;\n\t"⋯ 5 unchanged lines);}- __device__ __forceinline__ void tcgen05_mma_nvfp4(- uint64_t a_desc,- uint64_t b_desc,- uint32_t i_desc,- int scale_A_tmem,- int scale_B_tmem,- int enable_input_d- ) {- tcgen05_mma_nvfp4_d(0, a_desc, b_desc, i_desc, scale_A_tmem, scale_B_tmem, enable_input_d);- }-struct SHAPE { static constexpr char _16x256b[] = ".16x256b"; };- struct NUM {- static constexpr char x4[] = ".x4";- static constexpr char x8[] = ".x8";- };+ struct NUM { static constexpr char x8[] = ".x8"; };template <const char *SHAPE_, const char *NUM_>- __device__ __forceinline__ void tcgen05_ld_16regs(float *tmp, int row, int col) {- asm volatile(- "tcgen05.ld.sync.aligned%17%18.b32 "- "{ %0, %1, %2, %3, %4, %5, %6, %7, "- " %8, %9, %10, %11, %12, %13, %14, %15}, [%16];"- : "=f"(tmp[ 0]), "=f"(tmp[ 1]), "=f"(tmp[ 2]), "=f"(tmp[ 3]), "=f"(tmp[ 4]), "=f"(tmp[ 5]), "=f"(tmp[ 6]), "=f"(tmp[ 7]),- "=f"(tmp[ 8]), "=f"(tmp[ 9]), "=f"(tmp[10]), "=f"(tmp[11]), "=f"(tmp[12]), "=f"(tmp[13]), "=f"(tmp[14]), "=f"(tmp[15])- : "r"((row << 16) | col), "C"(SHAPE_), "C"(NUM_)- );- }-- template <const char *SHAPE_, const char *NUM_>__device__ __forceinline__ void tcgen05_ld_32regs(float *tmp, int row, int col) {asm volatile("tcgen05.ld.sync.aligned%33%34.b32 "⋯ 9 unchanged lines);}- __device__ __forceinline__ void tcgen05_ld_16x256bx4(float *tmp, int row, int col) {- tcgen05_ld_16regs<SHAPE::_16x256b, NUM::x4>(tmp, row, col);- }-__device__ __forceinline__ void tcgen05_ld_16x256bx8(float *tmp, int row, int col) {tcgen05_ld_32regs<SHAPE::_16x256b, NUM::x8>(tmp, row, col);}- __device__ __forceinline__ float silu_pos_fast(float x) {- // 仅对大正数分支优化：sigmoid(x)≈1 时直接返回 x，误差为 exp(-x)，相对误差 < 1e-3（x>7.75）- if (x > 7.75f) return x;- const float s = 1.0f / (1.0f + __expf(-x));- return x * s;- }-static inline void ck_cu(CUresult err) {if (err == CUDA_SUCCESS) return;const char *msg = nullptr;⋯ 1 unchanged linesTORCH_CHECK(false, msg);}- struct TmapKey {- uint64_t ptr;- uint64_t global_h;- uint64_t global_w;- uint32_t shared_h;- uint32_t shared_w;-- bool operator==(const TmapKey& other) const noexcept {- return ptr == other.ptr && global_h == other.global_h && global_w == other.global_w && shared_h == other.shared_h && shared_w == other.shared_w;- }- };-- struct TmapKeyHash {- size_t operator()(const TmapKey& k) const noexcept {- size_t h = std::hash<uint64_t>{}(k.ptr);- h = h * 1315423911u + std::hash<uint64_t>{}(k.global_h);- h = h * 1315423911u + std::hash<uint64_t>{}(k.global_w);- h = h * 1315423911u + std::hash<uint32_t>{}(k.shared_h);- h = h * 1315423911u + std::hash<uint32_t>{}(k.shared_w);- return h;- }- };-- static std::mutex g_tmap_mu;- static std::unordered_map<TmapKey, CUtensorMap, TmapKeyHash> g_tmap_cache;-static inline void init_AB_tmap(CUtensorMap *tmap,const char *ptr,uint64_t global_h, uint64_t global_w,uint32_t shared_h, uint32_t shared_w) {- const TmapKey key{- (uint64_t)ptr,- global_h,- global_w,- shared_h,- shared_w,- };+ constexpr uint32_t rank = 3;+ uint64_t globalDim[rank] = {256, global_h, global_w / 256};+ uint64_t globalStrides[rank-1] = {global_w / 2, 128};+ uint32_t boxDim[rank] = {256, shared_h, shared_w / 256};+ uint32_t elementStrides[rank] = {1, 1, 1};- {- std::lock_guard<std::mutex> lock(g_tmap_mu);- auto it = g_tmap_cache.find(key);- if (it != g_tmap_cache.end()) {- *tmap = it->second;- return;- }-- constexpr uint32_t rank = 3;- uint64_t globalDim[rank] = {256, global_h, global_w / 256};- uint64_t globalStrides[rank-1] = {global_w / 2, 128};- uint32_t boxDim[rank] = {256, shared_h, shared_w / 256};- uint32_t elementStrides[rank] = {1, 1, 1};-- CUtensorMap local;- auto err = cuTensorMapEncodeTiled(- &local,- CUtensorMapDataType::CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN8B,- rank,- (void *)ptr,- globalDim,- globalStrides,- boxDim,- elementStrides,- CUtensorMapInterleave::CU_TENSOR_MAP_INTERLEAVE_NONE,- CUtensorMapSwizzle::CU_TENSOR_MAP_SWIZZLE_128B,- CUtensorMapL2promotion::CU_TENSOR_MAP_L2_PROMOTION_NONE,- CUtensorMapFloatOOBfill::CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE- );- ck_cu(err);-- g_tmap_cache.emplace(key, local);- *tmap = local;- }+ auto err = cuTensorMapEncodeTiled(+ tmap,+ CUtensorMapDataType::CU_TENSOR_MAP_DATA_TYPE_16U4_ALIGN8B,+ rank,+ (void *)ptr,+ globalDim,+ globalStrides,+ boxDim,+ elementStrides,+ CUtensorMapInterleave::CU_TENSOR_MAP_INTERLEAVE_NONE,+ CUtensorMapSwizzle::CU_TENSOR_MAP_SWIZZLE_128B,+ CUtensorMapL2promotion::CU_TENSOR_MAP_L2_PROMOTION_NONE,+ CUtensorMapFloatOOBfill::CU_TENSOR_MAP_FLOAT_OOB_FILL_NONE+ );+ ck_cu(err);}template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>⋯ 12 unchanged linesconst int lane_id = tid & 31;const int warp_id = tid >> 5;+ const int grid_m = M / BLOCK_M;const int grid_n = N / BLOCK_N;const int bid_m = bid / grid_n;const int bid_n = bid - bid_m * grid_n;⋯ 32 unchanged linesif (warp_id == NUM_WARPS - 2 && elect_sync()) {const uint64_t cache_A = EVICT_LAST;- const uint64_t cache_B = EVICT_LAST;+ const uint64_t cache_B = EVICT_FIRST;auto issue_tma = [&](int iter_k, int stage_id) {const int mbar_addr = tma_mbar_addr + stage_id * 8;⋯ 93 unchanged linesfor (int mm = 0; mm < 2; mm++) {float tmp[BLOCK_N / 2];- if constexpr (BLOCK_N == 64) {- tcgen05_ld_16x256bx8(tmp, warp_id * 32 + mm * 16, 0);- asm volatile("tcgen05.wait::ld.sync.aligned;");- } else if constexpr (BLOCK_N == 128) {- tcgen05_ld_16x256bx8(tmp + 0, warp_id * 32 + mm * 16, 0);- tcgen05_ld_16x256bx8(tmp + 32, warp_id * 32 + mm * 16, 64);- asm volatile("tcgen05.wait::ld.sync.aligned;");- } else {- asm volatile("trap;");- }+ tcgen05_ld_16x256bx8(tmp, warp_id * 32 + mm * 16, 0);+ asm volatile("tcgen05.wait::ld.sync.aligned;");#pragma unrollfor (int i = 0; i < BLOCK_N / 8; i++) {⋯ 26 unchanged linesconst int lane_id = tid & 31;const int warp_id = tid >> 5;+ const int grid_m = M / BLOCK_M;const int grid_n = N / BLOCK_N;const int bid_m = bid / grid_n;const int bid_n = bid - bid_m * grid_n;⋯ 166 unchanged lines}template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>- __global__ __launch_bounds__(BLOCK_M + 2 * WARP_SIZE)- void dual_gemm_f32_kernel(- const __grid_constant__ CUtensorMap A_tmap,- const __grid_constant__ CUtensorMap B1_tmap,- const __grid_constant__ CUtensorMap B2_tmap,- const char *SFA_ptr,- const char *SFB1_ptr,- const char *SFB2_ptr,- float *G1_ptr,- float *G2_ptr,- int M, int N- ) {- const int tid = threadIdx.x;- const int bid = blockIdx.y;-- const int lane_id = tid & 31;- const int warp_id = tid >> 5;-- const int grid_n = N / BLOCK_N;- const int bid_m = bid / grid_n;- const int bid_n = bid - bid_m * grid_n;-- const int off_m = bid_m * BLOCK_M;- const int off_n = bid_n * BLOCK_N;-- constexpr int NUM_WARPS = BLOCK_M / WARP_SIZE + 2;-- extern __shared__ __align__(1024) char smem_ptr[];- const int smem = static_cast<int>(__cvta_generic_to_shared(smem_ptr));- constexpr int A_size = BLOCK_M * BLOCK_K / 2;- constexpr int B_size = BLOCK_N * BLOCK_K / 2;- constexpr int SFA_size = 128 * BLOCK_K / 16;- constexpr int SFB_size = 128 * BLOCK_K / 16;- constexpr int STAGE_SIZE = A_size + B_size + SFA_size + SFB_size;-- constexpr int MBAR_SET = NUM_STAGES * 2 + 1;- #pragma nv_diag_suppress static_var_with_dynamic_init- __shared__ int64_t mbars[MBAR_SET * 2];- const int base_mbar_addr = static_cast<int>(__cvta_generic_to_shared(mbars));-- const int tma_mbar_addr1 = base_mbar_addr;- const int mma_mbar_addr1 = tma_mbar_addr1 + NUM_STAGES * 8;- const int mainloop_mbar_addr1 = mma_mbar_addr1 + NUM_STAGES * 8;-- const int tma_mbar_addr2 = base_mbar_addr + MBAR_SET * 8;- const int mma_mbar_addr2 = tma_mbar_addr2 + NUM_STAGES * 8;- const int mainloop_mbar_addr2 = mma_mbar_addr2 + NUM_STAGES * 8;-- constexpr int SFA_tmem = BLOCK_N;- constexpr int SFB_tmem = SFA_tmem + 4 * (BLOCK_K / MMA_K);-- if (warp_id == 0 && elect_sync()) {- for (int i = 0; i < MBAR_SET * 2; i++) mbarrier_init(base_mbar_addr + i * 8, 1);- asm volatile("fence.mbarrier_init.release.cluster;");- } else if (warp_id == 1) {- asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(smem), "r"(BLOCK_N * 2));- }- __syncthreads();-- constexpr int num_iters = K / BLOCK_K;-- auto gemm_pass = [&](const CUtensorMap &B_tmap, const char *SFB_ptr, float *Out_ptr, int tma_mbar_addr, int mma_mbar_addr, int mainloop_mbar_addr) {- if (warp_id == NUM_WARPS - 2 && elect_sync()) {- const uint64_t cache_A = EVICT_LAST;- const uint64_t cache_B = EVICT_FIRST;-- auto issue_tma = [&](int iter_k, int stage_id) {- const int mbar_addr = tma_mbar_addr + stage_id * 8;- const int A_smem = smem + stage_id * STAGE_SIZE;- const int B_smem = A_smem + A_size;- const int SFA_smem = B_smem + B_size;- const int SFB_smem = SFA_smem + SFA_size;-- const int off_k = iter_k * BLOCK_K;- tma_3d_gmem2smem(A_smem, &A_tmap, 0, off_m, off_k / 256, mbar_addr, cache_A);- tma_3d_gmem2smem(B_smem, &B_tmap, 0, off_n, off_k / 256, mbar_addr, cache_B);-- const int rest_k = K / 16 / 4;- const char *SFA_src = SFA_ptr + ((off_m / 128) * rest_k + off_k / (16 * 4)) * 512;- const char *SFB_src = SFB_ptr + ((off_n / 128) * rest_k + off_k / (16 * 4)) * 512;- tma_gmem2smem(SFA_smem, SFA_src, SFA_size, mbar_addr, cache_A);- tma_gmem2smem(SFB_smem, SFB_src, SFB_size, mbar_addr, cache_B);-- asm volatile(- "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"- :: "r"(mbar_addr), "r"(STAGE_SIZE)- : "memory"- );- };-- constexpr int PRELOAD = (num_iters < NUM_STAGES) ? num_iters : NUM_STAGES;- for (int iter_k = 0; iter_k < PRELOAD; iter_k++) issue_tma(iter_k, iter_k);- for (int iter_k = NUM_STAGES; iter_k < num_iters; iter_k++) {- const int stage_id = iter_k % NUM_STAGES;- const int mma_phase = (iter_k / NUM_STAGES - 1) & 1;- mbarrier_wait(mma_mbar_addr + stage_id * 8, mma_phase);- issue_tma(iter_k, stage_id);- }- } else if (warp_id == NUM_WARPS - 1 && elect_sync()) {- constexpr int MMA_N = BLOCK_N;- constexpr int MMA_M = 128;- constexpr uint32_t i_desc = (1U << 7U) | (1U << 10U) | ((uint32_t)MMA_N >> 3U << 17U) | ((uint32_t)MMA_M >> 7U << 27U);-- for (int iter_k = 0; iter_k < num_iters; iter_k++) {- const int stage_id = iter_k % NUM_STAGES;- const int tma_phase = (iter_k / NUM_STAGES) & 1;- mbarrier_wait(tma_mbar_addr + stage_id * 8, tma_phase);-- const int A_smem = smem + stage_id * STAGE_SIZE;- const int B_smem = A_smem + A_size;- const int SFA_smem = B_smem + B_size;- const int SFB_smem = SFA_smem + SFA_size;-- auto make_desc_AB = [](int addr) -> uint64_t {- const int SBO = 8 * 128;- return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL) | (2ULL << 61ULL);- };- auto make_desc_SF = [](int addr) -> uint64_t {- const int SBO = 8 * 16;- return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL);- };-- constexpr uint64_t SF_desc = make_desc_SF(0);- const uint64_t SFA_desc = SF_desc + ((uint64_t)SFA_smem >> 4ULL);- const uint64_t SFB_desc = SF_desc + ((uint64_t)SFB_smem >> 4ULL);-- for (int k = 0; k < BLOCK_K / MMA_K; k++) {- uint64_t sfa_desc = SFA_desc + (uint64_t)k * (512ULL >> 4ULL);- uint64_t sfb_desc = SFB_desc + (uint64_t)k * (512ULL >> 4ULL);- tcgen05_cp_nvfp4(SFA_tmem + k * 4, sfa_desc);- tcgen05_cp_nvfp4(SFB_tmem + k * 4, sfb_desc);- }-- for (int k1 = 0; k1 < BLOCK_K / 256; k1++)- for (int k2 = 0; k2 < 256 / MMA_K; k2++) {- uint64_t a_desc = make_desc_AB(A_smem + k1 * BLOCK_M * 128 + k2 * 32);- uint64_t b_desc = make_desc_AB(B_smem + k1 * BLOCK_N * 128 + k2 * 32);-- const int k_sf = k1 * 4 + k2;- const int scale_A_tmem = SFA_tmem + k_sf * 4;- const int scale_B_tmem = SFB_tmem + k_sf * 4 + (bid_n % (128 / BLOCK_N)) * (BLOCK_N / 32);-- const int enable_input_d = (k1 == 0 && k2 == 0) ? iter_k : 1;- tcgen05_mma_nvfp4(a_desc, b_desc, i_desc, scale_A_tmem, scale_B_tmem, enable_input_d);- }-- asm volatile(- "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"- :: "r"(mma_mbar_addr + stage_id * 8)- : "memory"- );- }-- asm volatile(- "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"- :: "r"(mainloop_mbar_addr)- : "memory"- );- } else if (tid < BLOCK_M) {- mbarrier_wait(mainloop_mbar_addr, 0);- asm volatile("tcgen05.fence::after_thread_sync;");-- for (int mm = 0; mm < 2; mm++) {- float tmp[BLOCK_N / 2];- if constexpr (BLOCK_N == 64) {- tcgen05_ld_16x256bx8(tmp, warp_id * 32 + mm * 16, 0);- asm volatile("tcgen05.wait::ld.sync.aligned;");- } else if constexpr (BLOCK_N == 128) {- tcgen05_ld_16x256bx8(tmp + 0, warp_id * 32 + mm * 16, 0);- tcgen05_ld_16x256bx8(tmp + 32, warp_id * 32 + mm * 16, 64);- asm volatile("tcgen05.wait::ld.sync.aligned;");- } else {- asm volatile("trap;");- }-- #pragma unroll- for (int i = 0; i < BLOCK_N / 8; i++) {- const int row = off_m + warp_id * 32 + mm * 16 + lane_id / 4;- const int col = off_n + i * 8 + (lane_id & 3) * 2;- reinterpret_cast<float2 *>(Out_ptr + (row + 0) * N + col)[0] = float2{tmp[i * 4 + 0], tmp[i * 4 + 1]};- reinterpret_cast<float2 *>(Out_ptr + (row + 8) * N + col)[0] = float2{tmp[i * 4 + 2], tmp[i * 4 + 3]};- }- }- }- };-- gemm_pass(B1_tmap, SFB1_ptr, G1_ptr, tma_mbar_addr1, mma_mbar_addr1, mainloop_mbar_addr1);- __syncthreads();- gemm_pass(B2_tmap, SFB2_ptr, G2_ptr, tma_mbar_addr2, mma_mbar_addr2, mainloop_mbar_addr2);-- if (tid < BLOCK_M) {- asm volatile("bar.sync 1, %0;" :: "r"(BLOCK_M) : "memory");- if (warp_id == 0) asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(0), "r"(BLOCK_N * 2));- }- }-- template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>- __global__ __launch_bounds__(BLOCK_M + 2 * WARP_SIZE)- void fused_dual_gemm_silu_mul_kernel(- const __grid_constant__ CUtensorMap A_tmap,- const __grid_constant__ CUtensorMap B1_tmap,- const __grid_constant__ CUtensorMap B2_tmap,- const char *SFA_ptr,- const char *SFB1_ptr,- const char *SFB2_ptr,- half *Out_ptr,- int M, int N- ) {- const int tid = threadIdx.x;- const int bid = blockIdx.y;-- const int lane_id = tid & 31;- const int warp_id = tid >> 5;-- const int grid_n = N / BLOCK_N;- const int bid_m = bid / grid_n;- const int bid_n = bid - bid_m * grid_n;-- const int off_m = bid_m * BLOCK_M;- const int off_n = bid_n * BLOCK_N;-- constexpr int NUM_WARPS = BLOCK_M / WARP_SIZE + 2;-- extern __shared__ __align__(1024) char smem_ptr[];- const int smem = static_cast<int>(__cvta_generic_to_shared(smem_ptr));- constexpr int A_size = BLOCK_M * BLOCK_K / 2;- constexpr int B_size = BLOCK_N * BLOCK_K / 2;- constexpr int SFA_size = 128 * BLOCK_K / 16;- constexpr int SFB_size = 128 * BLOCK_K / 16;- constexpr int STAGE_SIZE = A_size + B_size + SFA_size + SFB_size;-- constexpr int MBAR_SET = NUM_STAGES * 2 + 1;- #pragma nv_diag_suppress static_var_with_dynamic_init- __shared__ int64_t mbars[MBAR_SET * 2];- const int base_mbar_addr = static_cast<int>(__cvta_generic_to_shared(mbars));-- const int tma_mbar_addr1 = base_mbar_addr;- const int mma_mbar_addr1 = tma_mbar_addr1 + NUM_STAGES * 8;- const int mainloop_mbar_addr1 = mma_mbar_addr1 + NUM_STAGES * 8;-- const int tma_mbar_addr2 = base_mbar_addr + MBAR_SET * 8;- const int mma_mbar_addr2 = tma_mbar_addr2 + NUM_STAGES * 8;- const int mainloop_mbar_addr2 = mma_mbar_addr2 + NUM_STAGES * 8;-- constexpr int SFA_tmem = BLOCK_N;- constexpr int SFB_tmem = SFA_tmem + 4 * (BLOCK_K / MMA_K);-- if (warp_id == 0 && elect_sync()) {- for (int i = 0; i < MBAR_SET * 2; i++) mbarrier_init(base_mbar_addr + i * 8, 1);- asm volatile("fence.mbarrier_init.release.cluster;");- } else if (warp_id == 1) {- asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(smem), "r"(BLOCK_N * 2));- }- __syncthreads();-- constexpr int num_iters = K / BLOCK_K;-- float2 g1_cache[BLOCK_N / 2];-- auto gemm_pass = [&](const CUtensorMap &B_tmap, const char *SFB_ptr, int tma_mbar_addr, int mma_mbar_addr, int mainloop_mbar_addr, int mode_store_g1) {- if (warp_id == NUM_WARPS - 2 && elect_sync()) {- const uint64_t cache_A = EVICT_LAST;- const uint64_t cache_B = EVICT_FIRST;-- auto issue_tma = [&](int iter_k, int stage_id) {- const int mbar_addr = tma_mbar_addr + stage_id * 8;- const int A_smem = smem + stage_id * STAGE_SIZE;- const int B_smem = A_smem + A_size;- const int SFA_smem = B_smem + B_size;- const int SFB_smem = SFA_smem + SFA_size;-- const int off_k = iter_k * BLOCK_K;- tma_3d_gmem2smem(A_smem, &A_tmap, 0, off_m, off_k / 256, mbar_addr, cache_A);- tma_3d_gmem2smem(B_smem, &B_tmap, 0, off_n, off_k / 256, mbar_addr, cache_B);-- const int rest_k = K / 16 / 4;- const char *SFA_src = SFA_ptr + ((off_m / 128) * rest_k + off_k / (16 * 4)) * 512;- const char *SFB_src = SFB_ptr + ((off_n / 128) * rest_k + off_k / (16 * 4)) * 512;- tma_gmem2smem(SFA_smem, SFA_src, SFA_size, mbar_addr, cache_A);- tma_gmem2smem(SFB_smem, SFB_src, SFB_size, mbar_addr, cache_B);-- asm volatile(- "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"- :: "r"(mbar_addr), "r"(STAGE_SIZE)- : "memory"- );- };-- constexpr int PRELOAD = (num_iters < NUM_STAGES) ? num_iters : NUM_STAGES;- for (int iter_k = 0; iter_k < PRELOAD; iter_k++) issue_tma(iter_k, iter_k);- for (int iter_k = NUM_STAGES; iter_k < num_iters; iter_k++) {- const int stage_id = iter_k % NUM_STAGES;- const int mma_phase = (iter_k / NUM_STAGES - 1) & 1;- mbarrier_wait(mma_mbar_addr + stage_id * 8, mma_phase);- issue_tma(iter_k, stage_id);- }- } else if (warp_id == NUM_WARPS - 1 && elect_sync()) {- constexpr int MMA_N = BLOCK_N;- constexpr int MMA_M = 128;- constexpr uint32_t i_desc = (1U << 7U) | (1U << 10U) | ((uint32_t)MMA_N >> 3U << 17U) | ((uint32_t)MMA_M >> 7U << 27U);-- for (int iter_k = 0; iter_k < num_iters; iter_k++) {- const int stage_id = iter_k % NUM_STAGES;- const int tma_phase = (iter_k / NUM_STAGES) & 1;- mbarrier_wait(tma_mbar_addr + stage_id * 8, tma_phase);-- const int A_smem = smem + stage_id * STAGE_SIZE;- const int B_smem = A_smem + A_size;- const int SFA_smem = B_smem + B_size;- const int SFB_smem = SFA_smem + SFA_size;-- auto make_desc_AB = [](int addr) -> uint64_t {- const int SBO = 8 * 128;- return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL) | (2ULL << 61ULL);- };- auto make_desc_SF = [](int addr) -> uint64_t {- const int SBO = 8 * 16;- return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL);- };-- constexpr uint64_t SF_desc = make_desc_SF(0);- const uint64_t SFA_desc = SF_desc + ((uint64_t)SFA_smem >> 4ULL);- const uint64_t SFB_desc = SF_desc + ((uint64_t)SFB_smem >> 4ULL);-- for (int k = 0; k < BLOCK_K / MMA_K; k++) {- uint64_t sfa_desc = SFA_desc + (uint64_t)k * (512ULL >> 4ULL);- uint64_t sfb_desc = SFB_desc + (uint64_t)k * (512ULL >> 4ULL);- tcgen05_cp_nvfp4(SFA_tmem + k * 4, sfa_desc);- tcgen05_cp_nvfp4(SFB_tmem + k * 4, sfb_desc);- }-- for (int k1 = 0; k1 < BLOCK_K / 256; k1++)- for (int k2 = 0; k2 < 256 / MMA_K; k2++) {- uint64_t a_desc = make_desc_AB(A_smem + k1 * BLOCK_M * 128 + k2 * 32);- uint64_t b_desc = make_desc_AB(B_smem + k1 * BLOCK_N * 128 + k2 * 32);-- const int k_sf = k1 * 4 + k2;- const int scale_A_tmem = SFA_tmem + k_sf * 4;- const int scale_B_tmem = SFB_tmem + k_sf * 4 + (bid_n % (128 / BLOCK_N)) * (BLOCK_N / 32);-- const int enable_input_d = (k1 == 0 && k2 == 0) ? iter_k : 1;- tcgen05_mma_nvfp4(a_desc, b_desc, i_desc, scale_A_tmem, scale_B_tmem, enable_input_d);- }-- asm volatile(- "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"- :: "r"(mma_mbar_addr + stage_id * 8)- : "memory"- );- }-- asm volatile(- "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"- :: "r"(mainloop_mbar_addr)- : "memory"- );- } else if (tid < BLOCK_M) {- mbarrier_wait(mainloop_mbar_addr, 0);- asm volatile("tcgen05.fence::after_thread_sync;");-- for (int mm = 0; mm < 2; mm++) {- float tmp[BLOCK_N / 2];- if constexpr (BLOCK_N == 64) {- tcgen05_ld_16x256bx8(tmp, warp_id * 32 + mm * 16, 0);- asm volatile("tcgen05.wait::ld.sync.aligned;");- } else if constexpr (BLOCK_N == 128) {- tcgen05_ld_16x256bx8(tmp + 0, warp_id * 32 + mm * 16, 0);- tcgen05_ld_16x256bx8(tmp + 32, warp_id * 32 + mm * 16, 64);- asm volatile("tcgen05.wait::ld.sync.aligned;");- } else {- asm volatile("trap;");- }-- #pragma unroll- for (int i = 0; i < BLOCK_N / 8; i++) {- const int base = mm * (BLOCK_N / 4) + i * 2;- if (mode_store_g1) {- g1_cache[base + 0] = float2{tmp[i * 4 + 0], tmp[i * 4 + 1]};- g1_cache[base + 1] = float2{tmp[i * 4 + 2], tmp[i * 4 + 3]};- } else {- const int row = off_m + warp_id * 32 + mm * 16 + lane_id / 4;- const int col = off_n + i * 8 + (lane_id & 3) * 2;- const float2 x0 = g1_cache[base + 0];- const float2 x8 = g1_cache[base + 1];- const float2 y0 = float2{tmp[i * 4 + 0], tmp[i * 4 + 1]};- const float2 y8 = float2{tmp[i * 4 + 2], tmp[i * 4 + 3]};-- float2 o0;- float2 o8;- const float s00 = 1.0f / (1.0f + __expf(-x0.x));- const float s01 = 1.0f / (1.0f + __expf(-x0.y));- const float s80 = 1.0f / (1.0f + __expf(-x8.x));- const float s81 = 1.0f / (1.0f + __expf(-x8.y));- o0.x = (x0.x * s00) * y0.x;- o0.y = (x0.y * s01) * y0.y;- o8.x = (x8.x * s80) * y8.x;- o8.y = (x8.y * s81) * y8.y;-- reinterpret_cast<half2 *>(Out_ptr + (row + 0) * N + col)[0] = __float22half2_rn(o0);- reinterpret_cast<half2 *>(Out_ptr + (row + 8) * N + col)[0] = __float22half2_rn(o8);- }- }- }- }- };-- gemm_pass(B1_tmap, SFB1_ptr, tma_mbar_addr1, mma_mbar_addr1, mainloop_mbar_addr1, 1);- __syncthreads();- gemm_pass(B2_tmap, SFB2_ptr, tma_mbar_addr2, mma_mbar_addr2, mainloop_mbar_addr2, 0);-- if (tid < BLOCK_M) {- asm volatile("bar.sync 1, %0;" :: "r"(BLOCK_M) : "memory");- if (warp_id == 0) asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(0), "r"(BLOCK_N * 2));- }- }-- template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>- __global__ __launch_bounds__(BLOCK_M + 2 * WARP_SIZE)- void fused_dual_gemm_silu_mul_kernel_v2(- const __grid_constant__ CUtensorMap A_tmap,- const __grid_constant__ CUtensorMap B1_tmap,- const __grid_constant__ CUtensorMap B2_tmap,- const char *SFA_ptr,- const char *SFB1_ptr,- const char *SFB2_ptr,- half *Out_ptr,- int M, int N- ) {- const int tid = threadIdx.x;-- const int lane_id = tid & 31;- const int warp_id = tid >> 5;-- const int bid_n = (int)blockIdx.x;- const int bid_m = (int)blockIdx.y;-- const int off_m = bid_m * BLOCK_M;- const int off_n = bid_n * BLOCK_N;-- constexpr int NUM_WARPS = BLOCK_M / WARP_SIZE + 2;-- extern __shared__ __align__(1024) char smem_ptr[];- const int smem = static_cast<int>(__cvta_generic_to_shared(smem_ptr));- constexpr int A_size = BLOCK_M * BLOCK_K / 2;- constexpr int B_size = BLOCK_N * BLOCK_K / 2;- constexpr int SFA_size = 128 * BLOCK_K / 16;- constexpr int SFB_size = 128 * BLOCK_K / 16;- constexpr int STAGE_SIZE = A_size + B_size + B_size + SFA_size + SFB_size + SFB_size;-- // 双 GEMM 拆分两路 TMA 屏障：让 B2/SFB2 的搬运尽量与 B1 计算重叠- constexpr int MBAR_SET = NUM_STAGES * 3 + 1;- #pragma nv_diag_suppress static_var_with_dynamic_init- __shared__ int64_t mbars[MBAR_SET];- const int base_mbar_addr = static_cast<int>(__cvta_generic_to_shared(mbars));-- const int tma1_mbar_addr = base_mbar_addr;- const int tma2_mbar_addr = tma1_mbar_addr + NUM_STAGES * 8;- const int mma_mbar_addr = tma2_mbar_addr + NUM_STAGES * 8;- const int mainloop_mbar_addr = mma_mbar_addr + NUM_STAGES * 8;-- constexpr int OUT1_tmem = 0;- constexpr int OUT2_tmem = BLOCK_N;- constexpr int SFA_tmem = 2 * BLOCK_N;- constexpr int SFB_tmem = SFA_tmem + 4 * (BLOCK_K / MMA_K);- constexpr int TMEM_ALLOC = 4 * BLOCK_N;-- if (warp_id == 0 && elect_sync()) {- for (int i = 0; i < MBAR_SET; i++) mbarrier_init(base_mbar_addr + i * 8, 1);- asm volatile("fence.mbarrier_init.release.cluster;");- } else if (warp_id == 1) {- asm volatile("tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%0], %1;" :: "r"(smem), "r"(TMEM_ALLOC));- }- __syncthreads();-- constexpr int num_iters = K / BLOCK_K;-- if (warp_id == NUM_WARPS - 2 && elect_sync()) {- const uint64_t cache_A = EVICT_LAST;- const uint64_t cache_B = EVICT_FIRST;-- auto issue_tma = [&](int iter_k, int stage_id) {- const int mbar1_addr = tma1_mbar_addr + stage_id * 8;- const int mbar2_addr = tma2_mbar_addr + stage_id * 8;- const int base = smem + stage_id * STAGE_SIZE;- const int A_smem = base;- const int B1_smem = A_smem + A_size;- const int B2_smem = B1_smem + B_size;- const int SFA_smem = B2_smem + B_size;- const int SFB1_smem = SFA_smem + SFA_size;- const int SFB2_smem = SFB1_smem + SFB_size;-- const int off_k = iter_k * BLOCK_K;- // phase1: A + B1 + SFA + SFB1- tma_3d_gmem2smem(A_smem, &A_tmap, 0, off_m, off_k / 256, mbar1_addr, cache_A);- tma_3d_gmem2smem(B1_smem, &B1_tmap, 0, off_n, off_k / 256, mbar1_addr, cache_B);-- const int rest_k = K / 16 / 4;- const char *SFA_src = SFA_ptr + ((off_m / 128) * rest_k + off_k / (16 * 4)) * 512;- const char *SFB1_src = SFB1_ptr + ((off_n / 128) * rest_k + off_k / (16 * 4)) * 512;- const char *SFB2_src = SFB2_ptr + ((off_n / 128) * rest_k + off_k / (16 * 4)) * 512;- tma_gmem2smem(SFA_smem, SFA_src, SFA_size, mbar1_addr, cache_A);- tma_gmem2smem(SFB1_smem, SFB1_src, SFB_size, mbar1_addr, cache_B);-- asm volatile(- "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"- :: "r"(mbar1_addr), "r"(A_size + B_size + SFA_size + SFB_size)- : "memory"- );-- // phase2: B2 + SFB2（尽量与 B1 计算重叠）- tma_3d_gmem2smem(B2_smem, &B2_tmap, 0, off_n, off_k / 256, mbar2_addr, cache_B);- tma_gmem2smem(SFB2_smem, SFB2_src, SFB_size, mbar2_addr, cache_B);- asm volatile(- "mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 _, [%0], %1;"- :: "r"(mbar2_addr), "r"(B_size + SFB_size)- : "memory"- );- };-- constexpr int PRELOAD = (num_iters < NUM_STAGES) ? num_iters : NUM_STAGES;- for (int iter_k = 0; iter_k < PRELOAD; iter_k++) issue_tma(iter_k, iter_k);- for (int iter_k = NUM_STAGES; iter_k < num_iters; iter_k++) {- const int stage_id = iter_k % NUM_STAGES;- const int mma_phase = (iter_k / NUM_STAGES - 1) & 1;- mbarrier_wait(mma_mbar_addr + stage_id * 8, mma_phase);- issue_tma(iter_k, stage_id);- }- } else if (warp_id == NUM_WARPS - 1 && elect_sync()) {- constexpr int MMA_N = BLOCK_N;- constexpr int MMA_M = 128;- constexpr uint32_t i_desc = (1U << 7U) | (1U << 10U) | ((uint32_t)MMA_N >> 3U << 17U) | ((uint32_t)MMA_M >> 7U << 27U);-- for (int iter_k = 0; iter_k < num_iters; iter_k++) {- const int stage_id = iter_k % NUM_STAGES;- const int tma_phase = (iter_k / NUM_STAGES) & 1;- mbarrier_wait(tma1_mbar_addr + stage_id * 8, tma_phase);-- const int base = smem + stage_id * STAGE_SIZE;- const int A_smem = base;- const int B1_smem = A_smem + A_size;- const int B2_smem = B1_smem + B_size;- const int SFA_smem = B2_smem + B_size;- const int SFB1_smem = SFA_smem + SFA_size;- const int SFB2_smem = SFB1_smem + SFB_size;-- auto make_desc_AB = [](int addr) -> uint64_t {- const int SBO = 8 * 128;- return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL) | (2ULL << 61ULL);- };- auto make_desc_SF = [](int addr) -> uint64_t {- const int SBO = 8 * 16;- return desc_encode(addr) | (desc_encode(SBO) << 32ULL) | (1ULL << 46ULL);- };-- constexpr uint64_t SF_desc = make_desc_SF(0);- const uint64_t SFA_desc = SF_desc + ((uint64_t)SFA_smem >> 4ULL);- const uint64_t SFB1_desc = SF_desc + ((uint64_t)SFB1_smem >> 4ULL);- const uint64_t SFB2_desc = SF_desc + ((uint64_t)SFB2_smem >> 4ULL);-- #pragma unroll- for (int k = 0; k < BLOCK_K / MMA_K; k++) {- uint64_t sfa_desc = SFA_desc + (uint64_t)k * (512ULL >> 4ULL);- tcgen05_cp_nvfp4(SFA_tmem + k * 4, sfa_desc);- }-- #pragma unroll- for (int k = 0; k < BLOCK_K / MMA_K; k++) {- uint64_t sfb_desc = SFB1_desc + (uint64_t)k * (512ULL >> 4ULL);- tcgen05_cp_nvfp4(SFB_tmem + k * 4, sfb_desc);- }-- int scale_B_off = 0;- if constexpr (BLOCK_N == 64) scale_B_off = (bid_n & 1) * 2;-- uint64_t a0, a1, a2, a3;- if constexpr (BLOCK_K == 256) {- const uint64_t a_base = make_desc_AB(A_smem);- a0 = a_base + 0;- a1 = a_base + 2;- a2 = a_base + 4;- a3 = a_base + 6;-- const uint64_t b1_base = make_desc_AB(B1_smem);- const uint64_t b10 = b1_base + 0;- const uint64_t b11 = b1_base + 2;- const uint64_t b12 = b1_base + 4;- const uint64_t b13 = b1_base + 6;-- tcgen05_mma_nvfp4_d(OUT1_tmem, a0, b10, i_desc, SFA_tmem + 0, SFB_tmem + 0 + scale_B_off, iter_k);- tcgen05_mma_nvfp4_d(OUT1_tmem, a1, b11, i_desc, SFA_tmem + 4, SFB_tmem + 4 + scale_B_off, 1);- tcgen05_mma_nvfp4_d(OUT1_tmem, a2, b12, i_desc, SFA_tmem + 8, SFB_tmem + 8 + scale_B_off, 1);- tcgen05_mma_nvfp4_d(OUT1_tmem, a3, b13, i_desc, SFA_tmem + 12, SFB_tmem + 12 + scale_B_off, 1);- } else {- #pragma unroll- for (int k1 = 0; k1 < BLOCK_K / 256; k1++) {- #pragma unroll- for (int k2 = 0; k2 < 256 / MMA_K; k2++) {- uint64_t a_desc = make_desc_AB(A_smem + k1 * BLOCK_M * 128 + k2 * 32);- uint64_t b_desc = make_desc_AB(B1_smem + k1 * BLOCK_N * 128 + k2 * 32);-- const int k_sf = k1 * 4 + k2;- const int scale_A_tmem = SFA_tmem + k_sf * 4;- const int scale_B_tmem = SFB_tmem + k_sf * 4 + scale_B_off;-- const int enable_input_d = (k1 == 0 && k2 == 0) ? iter_k : 1;- tcgen05_mma_nvfp4_d(OUT1_tmem, a_desc, b_desc, i_desc, scale_A_tmem, scale_B_tmem, enable_input_d);- }- }- }-- // 等到 B2/SFB2 就绪，再进入第二路 GEMM- mbarrier_wait(tma2_mbar_addr + stage_id * 8, tma_phase);-- #pragma unroll- for (int k = 0; k < BLOCK_K / MMA_K; k++) {- uint64_t sfb_desc = SFB2_desc + (uint64_t)k * (512ULL >> 4ULL);- tcgen05_cp_nvfp4(SFB_tmem + k * 4, sfb_desc);- }-- if constexpr (BLOCK_K == 256) {- const uint64_t b2_base = make_desc_AB(B2_smem);- const uint64_t b20 = b2_base + 0;- const uint64_t b21 = b2_base + 2;- const uint64_t b22 = b2_base + 4;- const uint64_t b23 = b2_base + 6;-- tcgen05_mma_nvfp4_d(OUT2_tmem, a0, b20, i_desc, SFA_tmem + 0, SFB_tmem + 0 + scale_B_off, iter_k);- tcgen05_mma_nvfp4_d(OUT2_tmem, a1, b21, i_desc, SFA_tmem + 4, SFB_tmem + 4 + scale_B_off, 1);- tcgen05_mma_nvfp4_d(OUT2_tmem, a2, b22, i_desc, SFA_tmem + 8, SFB_tmem + 8 + scale_B_off, 1);- tcgen05_mma_nvfp4_d(OUT2_tmem, a3, b23, i_desc, SFA_tmem + 12, SFB_tmem + 12 + scale_B_off, 1);- } else {- #pragma unroll- for (int k1 = 0; k1 < BLOCK_K / 256; k1++) {- #pragma unroll- for (int k2 = 0; k2 < 256 / MMA_K; k2++) {- uint64_t a_desc = make_desc_AB(A_smem + k1 * BLOCK_M * 128 + k2 * 32);- uint64_t b_desc = make_desc_AB(B2_smem + k1 * BLOCK_N * 128 + k2 * 32);-- const int k_sf = k1 * 4 + k2;- const int scale_A_tmem = SFA_tmem + k_sf * 4;- const int scale_B_tmem = SFB_tmem + k_sf * 4 + scale_B_off;-- const int enable_input_d = (k1 == 0 && k2 == 0) ? iter_k : 1;- tcgen05_mma_nvfp4_d(OUT2_tmem, a_desc, b_desc, i_desc, scale_A_tmem, scale_B_tmem, enable_input_d);- }- }- }-- asm volatile(- "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"- :: "r"(mma_mbar_addr + stage_id * 8)- : "memory"- );- }-- asm volatile(- "tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%0];"- :: "r"(mainloop_mbar_addr)- : "memory"- );- } else if (tid < BLOCK_M) {- mbarrier_wait(mainloop_mbar_addr, 0);- asm volatile("tcgen05.fence::after_thread_sync;");-- for (int mm = 0; mm < 2; mm++) {- const int row = off_m + warp_id * 32 + mm * 16 + lane_id / 4;- if constexpr (BLOCK_N == 64) {- #pragma unroll- for (int h = 0; h < 2; h++) {- float x_tmp[16];- float y_tmp[16];- const int col_t = h * 32;- tcgen05_ld_16x256bx4(x_tmp, warp_id * 32 + mm * 16, col_t);- tcgen05_ld_16x256bx4(y_tmp, warp_id * 32 + mm * 16, OUT2_tmem + col_t);- asm volatile("tcgen05.wait::ld.sync.aligned;");-- #pragma unroll- for (int i = 0; i < 4; i++) {- const int col = off_n + col_t + i * 8 + (lane_id & 3) * 2;- const float2 x0 = float2{x_tmp[i * 4 + 0], x_tmp[i * 4 + 1]};- const float2 x8 = float2{x_tmp[i * 4 + 2], x_tmp[i * 4 + 3]};- const float2 y0 = float2{y_tmp[i * 4 + 0], y_tmp[i * 4 + 1]};- const float2 y8 = float2{y_tmp[i * 4 + 2], y_tmp[i * 4 + 3]};-- float2 o0;- float2 o8;- o0.x = silu_pos_fast(x0.x) * y0.x;- o0.y = silu_pos_fast(x0.y) * y0.y;- o8.x = silu_pos_fast(x8.x) * y8.x;- o8.y = silu_pos_fast(x8.y) * y8.y;-- reinterpret_cast<half2 *>(Out_ptr + (row + 0) * N + col)[0] = __float22half2_rn(o0);- reinterpret_cast<half2 *>(Out_ptr + (row + 8) * N + col)[0] = __float22half2_rn(o8);- }- }- } else if constexpr (BLOCK_N == 128) {- #pragma unroll- for (int h = 0; h < 4; h++) {- float x_tmp[16];- float y_tmp[16];- const int col_t = h * 32;- tcgen05_ld_16x256bx4(x_tmp, warp_id * 32 + mm * 16, col_t);- tcgen05_ld_16x256bx4(y_tmp, warp_id * 32 + mm * 16, OUT2_tmem + col_t);- asm volatile("tcgen05.wait::ld.sync.aligned;");-- #pragma unroll- for (int i = 0; i < 4; i++) {- const int col = off_n + col_t + i * 8 + (lane_id & 3) * 2;- const float2 x0 = float2{x_tmp[i * 4 + 0], x_tmp[i * 4 + 1]};- const float2 x8 = float2{x_tmp[i * 4 + 2], x_tmp[i * 4 + 3]};- const float2 y0 = float2{y_tmp[i * 4 + 0], y_tmp[i * 4 + 1]};- const float2 y8 = float2{y_tmp[i * 4 + 2], y_tmp[i * 4 + 3]};-- float2 o0;- float2 o8;- o0.x = silu_pos_fast(x0.x) * y0.x;- o0.y = silu_pos_fast(x0.y) * y0.y;- o8.x = silu_pos_fast(x8.x) * y8.x;- o8.y = silu_pos_fast(x8.y) * y8.y;-- reinterpret_cast<half2 *>(Out_ptr + (row + 0) * N + col)[0] = __float22half2_rn(o0);- reinterpret_cast<half2 *>(Out_ptr + (row + 8) * N + col)[0] = __float22half2_rn(o8);- }- }- } else {- asm volatile("trap;");- }- }-- asm volatile("bar.sync 1, %0;" :: "r"(BLOCK_M) : "memory");- if (warp_id == 0) asm volatile("tcgen05.dealloc.cta_group::1.sync.aligned.b32 %0, %1;" :: "r"(0), "r"(TMEM_ALLOC));- }- }-- template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>- static inline void launch_fused_dual_gemm_silu_mul_v2(- const at::Tensor& A,- const at::Tensor& B1,- const at::Tensor& B2,- const at::Tensor& SFA,- const at::Tensor& SFB1,- const at::Tensor& SFB2,- at::Tensor& out- ) {- const int M = (int)A.size(0);- const int N = (int)B1.size(0);-- auto A_ptr = reinterpret_cast<const char *>(A.data_ptr());- auto B1_ptr = reinterpret_cast<const char *>(B1.data_ptr());- auto B2_ptr = reinterpret_cast<const char *>(B2.data_ptr());- auto SFA_ptr = reinterpret_cast<const char *>(SFA.data_ptr());- auto SFB1_ptr = reinterpret_cast<const char *>(SFB1.data_ptr());- auto SFB2_ptr = reinterpret_cast<const char *>(SFB2.data_ptr());- auto Out_ptr = reinterpret_cast<half *>(out.data_ptr());-- CUtensorMap A_tmap, B1_tmap, B2_tmap;- init_AB_tmap(&A_tmap, A_ptr, (uint64_t)M, (uint64_t)K, (uint32_t)BLOCK_M, (uint32_t)BLOCK_K);- init_AB_tmap(&B1_tmap, B1_ptr, (uint64_t)N, (uint64_t)K, (uint32_t)BLOCK_N, (uint32_t)BLOCK_K);- init_AB_tmap(&B2_tmap, B2_ptr, (uint64_t)N, (uint64_t)K, (uint32_t)BLOCK_N, (uint32_t)BLOCK_K);-- dim3 grid((unsigned)(N / BLOCK_N), (unsigned)(M / BLOCK_M));- const int tb_size = BLOCK_M + 2 * WARP_SIZE;-- const int A_size = BLOCK_M * (BLOCK_K / 2);- const int B_size = BLOCK_N * (BLOCK_K / 2);- const int SF_size = 128 * (BLOCK_K / 16);- const int stage_size = A_size + 2 * B_size + 3 * SF_size;- const int smem_size = stage_size * NUM_STAGES;-- auto kptr = fused_dual_gemm_silu_mul_kernel_v2<K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES>;- if (smem_size > 48'000) cudaFuncSetAttribute(kptr, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size);- kptr<<<grid, tb_size, smem_size>>>(A_tmap, B1_tmap, B2_tmap, SFA_ptr, SFB1_ptr, SFB2_ptr, Out_ptr, M, N);- }-- template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>static inline void launch_gemm_f32(const at::Tensor& A,const at::Tensor& B,⋯ 59 unchanged lineskptr<<<grid, tb_size, smem_size>>>(A_tmap, B_tmap, SFA_ptr, SFB_ptr, G1_ptr, Out_ptr, M, N);}- template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>- static inline void launch_dual_gemm_f32(- const at::Tensor& A,- const at::Tensor& B1,- const at::Tensor& B2,- const at::Tensor& SFA,- const at::Tensor& SFB1,- const at::Tensor& SFB2,- at::Tensor& g1,- at::Tensor& g2- ) {- const int M = (int)A.size(0);- const int N = (int)B1.size(0);-- auto A_ptr = reinterpret_cast<const char *>(A.data_ptr());- auto B1_ptr = reinterpret_cast<const char *>(B1.data_ptr());- auto B2_ptr = reinterpret_cast<const char *>(B2.data_ptr());- auto SFA_ptr = reinterpret_cast<const char *>(SFA.data_ptr());- auto SFB1_ptr = reinterpret_cast<const char *>(SFB1.data_ptr());- auto SFB2_ptr = reinterpret_cast<const char *>(SFB2.data_ptr());- auto G1_ptr = reinterpret_cast<float *>(g1.data_ptr());- auto G2_ptr = reinterpret_cast<float *>(g2.data_ptr());-- CUtensorMap A_tmap, B1_tmap, B2_tmap;- init_AB_tmap(&A_tmap, A_ptr, (uint64_t)M, (uint64_t)K, (uint32_t)BLOCK_M, (uint32_t)BLOCK_K);- init_AB_tmap(&B1_tmap, B1_ptr, (uint64_t)N, (uint64_t)K, (uint32_t)BLOCK_N, (uint32_t)BLOCK_K);- init_AB_tmap(&B2_tmap, B2_ptr, (uint64_t)N, (uint64_t)K, (uint32_t)BLOCK_N, (uint32_t)BLOCK_K);-- dim3 grid(1, (unsigned)((M / BLOCK_M) * (N / BLOCK_N)));- const int tb_size = BLOCK_M + 2 * WARP_SIZE;- const int AB_size = (BLOCK_M + BLOCK_N) * (BLOCK_K / 2);- const int SFAB_size = 128 * (BLOCK_K / 16) * 2;- const int smem_size = (AB_size + SFAB_size) * NUM_STAGES;-- auto kptr = dual_gemm_f32_kernel<K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES>;- if (smem_size > 48'000) cudaFuncSetAttribute(kptr, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size);- kptr<<<grid, tb_size, smem_size>>>(A_tmap, B1_tmap, B2_tmap, SFA_ptr, SFB1_ptr, SFB2_ptr, G1_ptr, G2_ptr, M, N);- }-- template <int K, int BLOCK_M, int BLOCK_N, int BLOCK_K, int NUM_STAGES>- static inline void launch_fused_dual_gemm_silu_mul(- const at::Tensor& A,- const at::Tensor& B1,- const at::Tensor& B2,- const at::Tensor& SFA,- const at::Tensor& SFB1,- const at::Tensor& SFB2,- at::Tensor& out- ) {- const int M = (int)A.size(0);- const int N = (int)B1.size(0);-- auto A_ptr = reinterpret_cast<const char *>(A.data_ptr());- auto B1_ptr = reinterpret_cast<const char *>(B1.data_ptr());- auto B2_ptr = reinterpret_cast<const char *>(B2.data_ptr());- auto SFA_ptr = reinterpret_cast<const char *>(SFA.data_ptr());- auto SFB1_ptr = reinterpret_cast<const char *>(SFB1.data_ptr());- auto SFB2_ptr = reinterpret_cast<const char *>(SFB2.data_ptr());- auto Out_ptr = reinterpret_cast<half *>(out.data_ptr());-- CUtensorMap A_tmap, B1_tmap, B2_tmap;- init_AB_tmap(&A_tmap, A_ptr, (uint64_t)M, (uint64_t)K, (uint32_t)BLOCK_M, (uint32_t)BLOCK_K);- init_AB_tmap(&B1_tmap, B1_ptr, (uint64_t)N, (uint64_t)K, (uint32_t)BLOCK_N, (uint32_t)BLOCK_K);- init_AB_tmap(&B2_tmap, B2_ptr, (uint64_t)N, (uint64_t)K, (uint32_t)BLOCK_N, (uint32_t)BLOCK_K);-- dim3 grid(1, (unsigned)((M / BLOCK_M) * (N / BLOCK_N)));- const int tb_size = BLOCK_M + 2 * WARP_SIZE;- const int AB_size = (BLOCK_M + BLOCK_N) * (BLOCK_K / 2);- const int SFAB_size = 128 * (BLOCK_K / 16) * 2;- const int smem_size = (AB_size + SFAB_size) * NUM_STAGES;-- auto kptr = fused_dual_gemm_silu_mul_kernel<K, BLOCK_M, BLOCK_N, BLOCK_K, NUM_STAGES>;- if (smem_size > 48'000) cudaFuncSetAttribute(kptr, cudaFuncAttributeMaxDynamicSharedMemorySize, smem_size);- kptr<<<grid, tb_size, smem_size>>>(A_tmap, B1_tmap, B2_tmap, SFA_ptr, SFB1_ptr, SFB2_ptr, Out_ptr, M, N);- }-__global__ void silu_mul_f32_vec2(const float* __restrict__ x, const float* __restrict__ y, half* __restrict__ out, int64_t n2) {const int64_t idx = int64_t(blockIdx.x) * blockDim.x + threadIdx.x;if (idx >= n2) return;⋯ 21 unchanged lines);}- at::Tensor fused_rank(- const at::Tensor& A,- const at::Tensor& B1,- const at::Tensor& B2,- const at::Tensor& SFA,- const at::Tensor& SFB1,- const at::Tensor& SFB2,- at::Tensor& out- ) {- TORCH_CHECK(A.is_cuda() && B1.is_cuda() && B2.is_cuda(), "cuda");- TORCH_CHECK(SFA.is_cuda() && SFB1.is_cuda() && SFB2.is_cuda(), "cuda");- TORCH_CHECK(out.is_cuda(), "cuda");- TORCH_CHECK(A.dim() == 3 && B1.dim() == 3 && B2.dim() == 3, "dim");- TORCH_CHECK(out.dim() == 3, "dim");-- const int64_t M = A.size(0);- const int64_t Kp = A.size(1);- const int64_t L = A.size(2);- const int64_t N = B1.size(0);- TORCH_CHECK(L == 1, "l");- TORCH_CHECK(B1.size(1) == Kp && B1.size(2) == L, "b1");- TORCH_CHECK(B2.size(1) == Kp && B2.size(2) == L, "b2");- TORCH_CHECK(out.size(0) == M && out.size(1) == N && out.size(2) == L, "out");-- TORCH_CHECK((M % 128) == 0, "m");- TORCH_CHECK((N % 64) == 0, "n");-- const int K = (int)(Kp * 2);-- // 计分区：单 kernel 融合双 GEMM + SiLU*Mul，避免中间写回- if (K == 7168) {- if (M == 512 && (N == 4096 || N == 3072)) {- launch_fused_dual_gemm_silu_mul_v2<7168, 128, 128, 256, 4>(A, B1, B2, SFA, SFB1, SFB2, out);- } else if (M == 256 && N == 4096) {- launch_fused_dual_gemm_silu_mul_v2<7168, 128, 64, 256, 5>(A, B1, B2, SFA, SFB1, SFB2, out);- } else {- TORCH_CHECK(false, "rank shape m,n ", M, " ", N);- }- } else if (K == 4096) {- if ((M == 256 || M == 512) && N == 3072) {- launch_fused_dual_gemm_silu_mul_v2<4096, 128, 64, 256, 5>(A, B1, B2, SFA, SFB1, SFB2, out);- } else {- TORCH_CHECK(false, "rank shape m,n ", M, " ", N);- }- } else {- TORCH_CHECK(false, "k ", K);- }-- return out;- }-at::Tensor fused(const at::Tensor& A,const at::Tensor& B1,⋯ 26 unchanged linesTORCH_CHECK((N % 64) == 0, "n");const int K = (int)(Kp * 2);- TORCH_CHECK(g1.scalar_type() == at::kFloat, "g1 dtype");- TORCH_CHECK(g2.scalar_type() == at::kFloat, "g2 dtype");-- // 计分区：优先减少 kernel 次数与 host 侧重复编码开销if (K == 7168) {- if (M == 256 && N == 4096) {- launch_dual_gemm_f32<7168, 128, 64, 512, 4>(A, B1, B2, SFA, SFB1, SFB2, g1, g2);- launch_silu_mul_f32(g1, g2, out);- } else {- if ((N % 128) == 0) {- launch_dual_gemm_f32<7168, 128, 128, 512, 3>(A, B1, B2, SFA, SFB1, SFB2, g1, g2);- } else {- launch_dual_gemm_f32<7168, 128, 64, 512, 4>(A, B1, B2, SFA, SFB1, SFB2, g1, g2);- }- launch_silu_mul_f32(g1, g2, out);- }+ launch_gemm_f32<7168, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);+ launch_gemm_silu_mul<7168, 128, 64, 256, 8>(A, B2, SFA, SFB2, g1, out);} else if (K == 4096) {- launch_dual_gemm_f32<4096, 128, 64, 512, 4>(A, B1, B2, SFA, SFB1, SFB2, g1, g2);- launch_silu_mul_f32(g1, g2, out);+ launch_gemm_f32<4096, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);+ launch_gemm_silu_mul<4096, 128, 64, 256, 8>(A, B2, SFA, SFB2, g1, out);} else if (K == 2304) {launch_gemm_f32<2304, 128, 64, 256, 8>(A, B1, SFA, SFB1, g1);- launch_gemm_f32<2304, 128, 64, 256, 8>(A, B2, SFA, SFB2, g2);- launch_silu_mul_f32(g1, g2, out);⋯ diff truncated
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