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submission 614241

dannywillowliu-uchi · python · License unknown

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Vendorable · source mirrored · license unknownView source →

No package. Vendor the mirrored source: 139 lines, June 9 Researcher Reciprocity License v1.0.

submission.py
curl "https://kernelindex.com/api/v1/implementations/kernelbot-histogram-v2-614241?include=source"
interfacepython
Compatibility
measured onNVIDIA B200
declared hardwareNVIDIA B200
architecturessm_100
dtypesuint8

Benchmark evidence

1 measurement across 1 GPU, fastest first.

Operation / workload
Hardware
Latency
Rank
Observed
Histogramsuite of 6 cases
NVIDIA B200
12.3µs
#7 of 54
2026-03-23

Reported · How evidence levels are derived →

Source and license

sourceavailable
revision digestsha256:64a4284f6a1fd7e4a93b512421ac41af17caf927ec6ff6448132789c949cbb07
license declaredunknown
license concludedunknown
authorsdannywillowliu-uchi
imported2026-08-15

Techniques

Extracted from the mirrored source by pattern, never inferred. Each row cites its line.

shared-memory__shared__ uint32_t smem[WSUB * 256];
vector-width = uint4const uint4* data_vec = (const uint4*)data;

Kernel source

submission.py139 lines
import os
os.environ["CUBLAS_WORKSPACE_CONFIG"] = ":4096:8"

import torch
from torch.utils.cpp_extension import load_inline
from task import input_t, output_t

cuda_source = r"""
#include <torch/extension.h>
#include <cuda_runtime.h>
#include <cstdint>

__global__ __launch_bounds__(512)
void histogram_custom(
    const uint8_t* __restrict__ data,
    int64_t* __restrict__ output,
    const int64_t n
) {
    constexpr int WSUB = 8;
    __shared__ uint32_t smem[WSUB * 256];

    const int warp_id = threadIdx.x >> 5;

    // Fused zero: block 0 zeros output (eliminates separate memset kernel)
    if (blockIdx.x == 0 && threadIdx.x < 256) {
        output[threadIdx.x] = 0;
    }

    #pragma unroll
    for (int i = threadIdx.x; i < WSUB * 256; i += 512) {
        smem[i] = 0;
    }
    __syncthreads();

    if (blockIdx.x == 0 && threadIdx.x == 0) {
        __threadfence();
    }

    uint32_t* my_hist = smem + (warp_id & 7) * 256;

    const int64_t tid = blockIdx.x * 512 + threadIdx.x;
    const int64_t grid_stride = 512LL * gridDim.x;

    const int64_t n16 = n >> 4;
    const uint4* data_vec = (const uint4*)data;

    for (int64_t i = tid; i < n16; i += grid_stride) {
        uint4 vals = __ldg(&data_vec[i]);

        atomicAdd(&my_hist[(vals.x      ) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.x >>  8) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.x >> 16) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.x >> 24)       ], 1u);
        atomicAdd(&my_hist[(vals.y      ) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.y >>  8) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.y >> 16) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.y >> 24)       ], 1u);
        atomicAdd(&my_hist[(vals.z      ) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.z >>  8) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.z >> 16) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.z >> 24)       ], 1u);
        atomicAdd(&my_hist[(vals.w      ) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.w >>  8) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.w >> 16) & 0xFF], 1u);
        atomicAdd(&my_hist[(vals.w >> 24)       ], 1u);
    }

    {
        int64_t tail_start = n16 * 16;
        for (int64_t i = tail_start + tid; i < n; i += grid_stride) {
            atomicAdd(&my_hist[__ldg(&data[i])], 1u);
        }
    }

    __syncthreads();

    if (threadIdx.x < 256) {
        uint32_t total = 0;
        #pragma unroll
        for (int w = 0; w < WSUB; w++) {
            total += smem[w * 256 + threadIdx.x];
        }
        if (total > 0) {
            atomicAdd((unsigned long long*)&output[threadIdx.x], (unsigned long long)total);
        }
    }
}

static int _sm_count = -1;

int get_sm_count() {
    if (_sm_count < 0) {
        cudaDeviceProp prop;
        cudaGetDeviceProperties(&prop, 0);
        _sm_count = prop.multiProcessorCount;
    }
    return _sm_count;
}

torch::Tensor histogram_cuda(torch::Tensor data, torch::Tensor output) {
    const int64_t n = data.numel();

    int blocks = get_sm_count();

    histogram_custom<<<blocks, 512>>>(
        data.data_ptr<uint8_t>(),
        output.data_ptr<int64_t>(),
        n
    );

    return output;
}
""";

cpp_source = r"""
torch::Tensor histogram_cuda(torch::Tensor data, torch::Tensor output);
""";

module = load_inline(
    name="histogram_submit_fused",
    cpp_sources=[cpp_source],
    cuda_sources=[cuda_source],
    functions=["histogram_cuda"],
    verbose=False,
    extra_cuda_cflags=["-O3", "--use_fast_math"],
)

_wd = torch.randint(0, 256, (1024,), device="cuda", dtype=torch.uint8)
_wo = torch.zeros(256, device="cuda", dtype=torch.int64)
module.histogram_cuda(_wd, _wo)
torch.cuda.synchronize()
del _wd, _wo


def custom_kernel(data: input_t) -> output_t:
    data_tensor, output = data
    module.histogram_cuda(data_tensor, output)
    return output
scrolls · 139 lines total

Source code from GPU Mode and the KernelBot dataset · June 9 Researcher Reciprocity License v1.0

Changes from previous submission

Against this author's previous submission submission 614126.

⋯ 15 unchanged lines
int64_t* __restrict__ output,
const int64_t n
) {
- constexpr int WARPS = 16;
- __shared__ uint32_t smem[WARPS * 256];
+ constexpr int WSUB = 8;
+ __shared__ uint32_t smem[WSUB * 256];
const int warp_id = threadIdx.x >> 5;
+ // Fused zero: block 0 zeros output (eliminates separate memset kernel)
+ if (blockIdx.x == 0 && threadIdx.x < 256) {
+ output[threadIdx.x] = 0;
+ }
+
#pragma unroll
- for (int i = threadIdx.x; i < WARPS * 256; i += 512) {
+ for (int i = threadIdx.x; i < WSUB * 256; i += 512) {
smem[i] = 0;
}
__syncthreads();
- uint32_t* my_hist = smem + warp_id * 256;
+ if (blockIdx.x == 0 && threadIdx.x == 0) {
+ __threadfence();
+ }
+ uint32_t* my_hist = smem + (warp_id & 7) * 256;
+
const int64_t tid = blockIdx.x * 512 + threadIdx.x;
const int64_t grid_stride = 512LL * gridDim.x;
⋯ 33 unchanged lines
if (threadIdx.x < 256) {
uint32_t total = 0;
#pragma unroll
- for (int w = 0; w < WARPS; w++) {
+ for (int w = 0; w < WSUB; w++) {
total += smem[w * 256 + threadIdx.x];
}
if (total > 0) {
⋯ 15 unchanged lines
torch::Tensor histogram_cuda(torch::Tensor data, torch::Tensor output) {
const int64_t n = data.numel();
- cudaMemsetAsync(output.data_ptr<int64_t>(), 0, 256 * sizeof(int64_t));
- int blocks = get_sm_count() * 2;
+ int blocks = get_sm_count();
- if (n < 512 * 16 * blocks) {
- blocks = (n + 512 * 16 - 1) / (512 * 16);
- if (blocks < 1) blocks = 1;
- }
-
histogram_custom<<<blocks, 512>>>(
data.data_ptr<uint8_t>(),
output.data_ptr<int64_t>(),
⋯ 9 unchanged lines
""";
module = load_inline(
- name="histogram_submit_final",
+ name="histogram_submit_fused",
cpp_sources=[cpp_source],
cuda_sources=[cuda_source],
functions=["histogram_cuda"],
scrolls · 68 diff lines total

Best evidence level for this revision: reported

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