submission 714495
Danishlynx · python · License unknown
Use it
Vendorable · source mirrored · license unknownView source →
No package. Vendor the mirrored source: 233 lines, June 9 Researcher Reciprocity License v1.0.
submission.py
curl "https://kernelindex.com/api/v1/implementations/kernelbot-amd-moe-mxfp4-714495?include=source"interfacepython
Compatibility
measured onAMD Instinct MI355X
declared hardwareAMD Instinct MI355X
architecturesgfx950
dtypesbf16, fp32, fp8_e8m0, int32, mxfp4
Benchmark evidence
1 measurement across 1 GPU, fastest first.
Operation / workload
Hardware
Latency
Rank
Observed
Reported · How evidence levels are derived →
Source and license
sourceavailable
revision digestsha256:47c7e031b22472b53eae32087bb8908a044f7f22a15c66f16d6ef5e871dd9fba
license declaredunknown
license concludedunknown
authorsDanishlynx
imported2026-08-15
Techniques
Extracted from the mirrored source by pattern, never inferred. Each row cites its line.
Kernel source
submission.py233 lines
# /// script
# leaderboard = "amd-moe-mxfp4"
# ///
"""v913: FlyDSL for BOTH stages — the breakthrough.
flydsl 0.1.1 fixes scf.yield bug. FlyDSL stage1 replaces CK stage1.
Expected: -10 to -20μs (122→102-112μs)."""
import os, sys, torch, subprocess, shutil, re, functools
os.environ['HIP_FORCE_DEV_KERNARG'] = '1'
os.environ['AITER_ENABLE_VSKIP'] = '1'
os.environ['AMD_DIRECT_DISPATCH'] = '1'
os.environ['GPU_MAX_HW_QUEUES'] = '8'
os.environ['HSA_ENABLE_SDMA'] = '0'
os.environ['HIP_LAUNCH_BLOCKING'] = '0'
os.environ['AMD_SERIALIZE_KERNEL'] = '0'
os.environ['GPU_SINGLE_ALLOC_PERCENT'] = '100'
os.environ['HSA_SVM_GUARD_PAGES'] = '0'
_AITER_DIR = '/home/runner/aiter'
_NEW_DIR = '/tmp/aiter_fresh'
_FLYDSL_DIR = '/tmp/flydsl_new'
# ========== STEP 1: Install flydsl 0.1.1 ==========
os.makedirs(_FLYDSL_DIR, exist_ok=True)
subprocess.run([sys.executable, '-m', 'pip', 'install', 'flydsl==0.1.1',
'--target', _FLYDSL_DIR, '--upgrade', '--break-system-packages'],
capture_output=True, text=True, timeout=120)
sys.path.insert(0, _FLYDSL_DIR)
for key in list(sys.modules.keys()):
if 'flydsl' in key:
del sys.modules[key]
import flydsl
print(f"[v913] flydsl {flydsl.__version__}", file=sys.stderr)
# ========== STEP 2: Setup AITER ==========
subprocess.run(['git', 'checkout', '--', '.'], capture_output=True, cwd=_AITER_DIR, timeout=10)
if not os.path.exists(os.path.join(_NEW_DIR, 'aiter')):
subprocess.run(['git', 'clone', '--depth=1', 'https://github.com/ROCm/aiter.git', _NEW_DIR],
capture_output=True, text=True, timeout=120)
# Copy newer fused_moe.py
shutil.copy2(os.path.join(_NEW_DIR, 'aiter', 'fused_moe.py'),
os.path.join(_AITER_DIR, 'aiter', 'fused_moe.py'))
# Copy safe flydsl files (NOT gemm_kernels.py which needs flydsl.expr)
flydsl_src = os.path.join(_NEW_DIR, 'aiter', 'ops', 'flydsl')
flydsl_dst = os.path.join(_AITER_DIR, 'aiter', 'ops', 'flydsl')
for fname in ['moe_kernels.py', 'utils.py']:
shutil.copy2(os.path.join(flydsl_src, fname), os.path.join(flydsl_dst, fname))
# Patch __init__.py version check
init_path = os.path.join(flydsl_dst, '__init__.py')
with open(init_path) as f:
init_src = f.read()
init_src = re.sub(r'raise ImportError\([^)]*\)', 'pass # version check bypassed', init_src)
with open(init_path, 'w') as f:
f.write(init_src)
# Copy MLIR kernel generators
kernels_src = os.path.join(flydsl_src, 'kernels')
kernels_dst = os.path.join(flydsl_dst, 'kernels')
if os.path.exists(kernels_src):
os.makedirs(kernels_dst, exist_ok=True)
for fname in os.listdir(kernels_src):
if fname.endswith('.py'):
shutil.copy2(os.path.join(kernels_src, fname), os.path.join(kernels_dst, fname))
# ========== STEP 3: Source patches ==========
_FMOE_PATH = os.path.join(_AITER_DIR, 'aiter', 'fused_moe.py')
with open(_FMOE_PATH, 'r') as f:
src = f.read()
src = src.replace('split_k=ksplit', 'split_k=2')
src = src.replace('splitk=ksplit', 'splitk=2')
# Minimal block_m override
bm_marker = 'def get_block_size_M(token, topk, expert, inter_dim):'
if bm_marker in src:
dec_search = src.rfind('@functools.lru_cache', 0, src.index(bm_marker))
start = dec_search if dec_search >= 0 else src.index(bm_marker)
lines_bm = src[src.index(bm_marker):].split('\n')
end_offset = 0; found_body = False
for i, line in enumerate(lines_bm):
if i == 0: end_offset += len(line) + 1; continue
stripped = line.strip()
if stripped == '' or stripped.startswith('#'): end_offset += len(line) + 1; continue
if found_body and (not line.startswith(' ') and not line.startswith('\t') and stripped != ''): break
if line.startswith(' ') or line.startswith('\t'): found_body = True
end_offset += len(line) + 1
end = src.index(bm_marker) + end_offset
new_bm = '''@functools.lru_cache(maxsize=2048)
def get_block_size_M(token, topk, expert, inter_dim):
_ov = {(512,9,33,512): 128}
key = (token, topk, expert, inter_dim)
if key in _ov: return _ov[key]
cu_num = get_cu_num(); tileN = 128; tgN = (inter_dim + tileN - 1) // tileN
tmp = []
for el in [32, 64, 128]:
mnt = token * topk + expert * el - topk; tg = tgN * (mnt + el - 1) // el
tmp.append(((tg + cu_num - 1) // cu_num, cu_num - tg % cu_num, el))
return sorted(tmp, key=lambda x: x[:2])[0][-1]
'''
src = src[:start] + new_bm + src[end:]
# Append FlyDSL stage1 + stage2 wrappers
tail = r'''
# v913: FlyDSL BOTH stages
def _v913_fly_s1(hidden_states, w1, w2, sorted_token_ids, sorted_expert_ids, num_valid_ids, out, topk, w1_scale=None, a1_scale=None, sorted_weights=None, **_kw):
from aiter.ops.flydsl.moe_kernels import flydsl_moe_stage1
flydsl_moe_stage1(a=hidden_states, w1=w1, sorted_token_ids=sorted_token_ids,
sorted_expert_ids=sorted_expert_ids, num_valid_ids=num_valid_ids, out=out, topk=topk,
tile_m=32, tile_n=256, tile_k=128, a_dtype="fp4", b_dtype="fp4", out_dtype="bf16",
act="silu", w1_scale=w1_scale, a1_scale=a1_scale, sorted_weights=sorted_weights)
return out # flydsl writes in-place, but caller expects return value
def _v913_fly_s2_direct(inter_states, w1, w2, sorted_token_ids, sorted_expert_ids, num_valid_ids, out, topk, w2_scale=None, a2_scale=None, sorted_weights=None, **_kw):
from aiter.ops.flydsl.moe_kernels import flydsl_moe_stage2
flydsl_moe_stage2(inter_states=inter_states, w2=w2, sorted_token_ids=sorted_token_ids,
sorted_expert_ids=sorted_expert_ids, num_valid_ids=num_valid_ids, out=out, topk=topk,
tile_m=16, tile_n=256, tile_k=128, a_dtype="fp4", b_dtype="fp4", out_dtype="bf16",
mode="direct", w2_scale=w2_scale, a2_scale=a2_scale, sorted_weights=sorted_weights)
def _v913_fly_s2_atomic(inter_states, w1, w2, sorted_token_ids, sorted_expert_ids, num_valid_ids, out, topk, w2_scale=None, a2_scale=None, sorted_weights=None, **_kw):
from aiter.ops.flydsl.moe_kernels import flydsl_moe_stage2
flydsl_moe_stage2(inter_states=inter_states, w2=w2, sorted_token_ids=sorted_token_ids,
sorted_expert_ids=sorted_expert_ids, num_valid_ids=num_valid_ids, out=out, topk=topk,
tile_m=16, tile_n=256, tile_k=128, a_dtype="fp4", b_dtype="fp4", out_dtype="bf16",
mode="atomic", w2_scale=w2_scale, a2_scale=a2_scale, sorted_weights=sorted_weights)
_v913_orig_g2sc = get_2stage_cfgs
try: _v913_orig_g2sc.cache_clear()
except: pass
_v913_fly_ready = [False]
_v913_s1_ready = [False]
@functools.lru_cache(maxsize=2048)
def _v913_g2sc(*a, **kw):
md = _v913_orig_g2sc(*a, **kw)
if len(a) >= 5:
E_val = a[4]; bs_val = a[1]
if E_val <= 100 and bs_val >= 512:
md.use_non_temporal_load = True
# Replace stage1 with FlyDSL (if compiled)
if _v913_s1_ready[0] and not md.run_1stage and md.stage1 is not None:
md.stage1 = functools.partial(_v913_fly_s1)
elif not md.run_1stage and md.stage1 is not None:
_orig_s1 = md.stage1
def _s1w(*aa, **kk):
kk['splitk'] = 2
return _orig_s1(*aa, **kk)
md.stage1 = _s1w
# Replace stage2 with FlyDSL
if _v913_fly_ready[0] and not md.run_1stage and md.stage2 is not None:
E_val = a[4] if len(a) >= 5 else 0
md.stage2 = functools.partial(_v913_fly_s2_atomic if E_val > 100 else _v913_fly_s2_direct)
return md
get_2stage_cfgs = _v913_g2sc
import sys as _s
print("[v913] FlyDSL BOTH stages patched", file=_s.stderr)
'''
src += tail
with open(_FMOE_PATH, 'w') as f:
f.write(src)
# ========== STEP 4: Import ==========
from aiter import ActivationType, QuantType
from aiter.fused_moe import fused_moe
import aiter.fused_moe as _fmoe
from task import input_t, output_t
# ========== STEP 5: Pre-compile FlyDSL ==========
try:
from aiter.ops.flydsl.moe_kernels import _get_compiled_stage1, _get_compiled_stage2
# Stage1 for all shapes
for inter, exp in [(256, 257), (512, 33), (2048, 33)]:
try:
_get_compiled_stage1(model_dim=7168, inter_dim=inter, experts=exp, topk=9,
tile_m=32, tile_n=256, tile_k=128, doweight=True,
a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", act="silu")
print(f"[v913] Stage1 compiled: inter={inter} E={exp}", file=sys.stderr)
except Exception as e:
print(f"[v913] Stage1 FAILED inter={inter} E={exp}: {str(e)[:100]}", file=sys.stderr)
_fmoe._v913_s1_ready[0] = True
print("[v913] FlyDSL STAGE1 ENABLED!", file=sys.stderr)
# Stage2 for all shapes
_get_compiled_stage2(model_dim=7168, inter_dim=256, experts=257, topk=9,
tile_m=16, tile_n=256, tile_k=128, doweight=True,
a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", accumulate=True)
try:
_get_compiled_stage2(model_dim=7168, inter_dim=256, experts=257, topk=9,
tile_m=16, tile_n=256, tile_k=128, doweight=True,
a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", accumulate=True, mode="atomic")
except: pass
for d in [512, 2048]:
_get_compiled_stage2(model_dim=7168, inter_dim=d, experts=33, topk=9,
tile_m=16, tile_n=256, tile_k=128, doweight=True,
a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", accumulate=True)
_fmoe._v913_fly_ready[0] = True
print("[v913] FlyDSL STAGE2 ENABLED!", file=sys.stderr)
except Exception as e:
print(f"[v913] Pre-compile failed: {e}", file=sys.stderr)
import traceback; traceback.print_exc(file=sys.stderr)
# Per-shape warmup
_warmed = set()
def _warmup(data):
(hs, guw, dw, guws, dws, guw_sh, dw_sh, guws_sh, dws_sh, tw, ti, cfg) = data
key = (cfg["bs"], cfg["n_routed_experts"], cfg["d_expert"])
if key in _warmed: return
_warmed.add(key)
try:
_ = fused_moe(hs[:2], guw_sh, dw_sh, tw[:2], ti[:2],
activation=ActivationType.Silu, quant_type=QuantType.per_1x32,
w1_scale=guws_sh, w2_scale=dws_sh,
hidden_pad=cfg["d_hidden_pad"]-cfg["d_hidden"],
intermediate_pad=cfg["d_expert_pad"]-cfg["d_expert"])
torch.cuda.synchronize()
except: pass
def custom_kernel(data: input_t) -> output_t:
_warmup(data)
(hs, guw, dw, guws, dws, guw_sh, dw_sh, guws_sh, dws_sh, tw, ti, cfg) = data
return fused_moe(hs, guw_sh, dw_sh, tw, ti,
activation=ActivationType.Silu, quant_type=QuantType.per_1x32,
w1_scale=guws_sh, w2_scale=dws_sh,
hidden_pad=cfg["d_hidden_pad"]-cfg["d_hidden"],
intermediate_pad=cfg["d_expert_pad"]-cfg["d_expert"])
scrolls · 233 lines total
Source code from GPU Mode and the KernelBot dataset · June 9 Researcher Reciprocity License v1.0
Changes from previous submission
Against this author's previous submission submission 589916.
# /// script# leaderboard = "amd-moe-mxfp4"# ///- """v209: tile_m=16 ALL (proven better for E=33) + sort cache + quant cache.- v200 (tm16all+sort): bench ~132. v206 (v99tm+sort+quant): bench ~127.- v209 should combine best of both: tm16all for E=33 gains + quant cache for E=257 gains.- """- import os; os.environ["AITER_USE_NT"] = "1"- import sys, torch, functools- from task import input_t, output_t- from aiter import ActivationType, QuantType- from aiter.fused_moe import fused_moe- import aiter.fused_moe as _fmoe+ """v913: FlyDSL for BOTH stages — the breakthrough.+ flydsl 0.1.1 fixes scf.yield bug. FlyDSL stage1 replaces CK stage1.+ Expected: -10 to -20μs (122→102-112μs)."""+ import os, sys, torch, subprocess, shutil, re, functools- def P(*a): print(*a, file=sys.stderr, flush=True)+ os.environ['HIP_FORCE_DEV_KERNARG'] = '1'+ os.environ['AITER_ENABLE_VSKIP'] = '1'+ os.environ['AMD_DIRECT_DISPATCH'] = '1'+ os.environ['GPU_MAX_HW_QUEUES'] = '8'+ os.environ['HSA_ENABLE_SDMA'] = '0'+ os.environ['HIP_LAUNCH_BLOCKING'] = '0'+ os.environ['AMD_SERIALIZE_KERNEL'] = '0'+ os.environ['GPU_SINGLE_ALLOC_PERCENT'] = '100'+ os.environ['HSA_SVM_GUARD_PAGES'] = '0'- _bm_ov = {(128,9,33,512):32,(128,9,33,2048):32,(512,9,33,512):64,(512,9,33,2048):64,(512,9,257,256):64}- @functools.lru_cache(maxsize=2048)- def _bm(token, topk, expert, inter_dim):+ _AITER_DIR = '/home/runner/aiter'+ _NEW_DIR = '/tmp/aiter_fresh'+ _FLYDSL_DIR = '/tmp/flydsl_new'++ # ========== STEP 1: Install flydsl 0.1.1 ==========+ os.makedirs(_FLYDSL_DIR, exist_ok=True)+ subprocess.run([sys.executable, '-m', 'pip', 'install', 'flydsl==0.1.1',+ '--target', _FLYDSL_DIR, '--upgrade', '--break-system-packages'],+ capture_output=True, text=True, timeout=120)+ sys.path.insert(0, _FLYDSL_DIR)+ for key in list(sys.modules.keys()):+ if 'flydsl' in key:+ del sys.modules[key]+ import flydsl+ print(f"[v913] flydsl {flydsl.__version__}", file=sys.stderr)++ # ========== STEP 2: Setup AITER ==========+ subprocess.run(['git', 'checkout', '--', '.'], capture_output=True, cwd=_AITER_DIR, timeout=10)++ if not os.path.exists(os.path.join(_NEW_DIR, 'aiter')):+ subprocess.run(['git', 'clone', '--depth=1', 'https://github.com/ROCm/aiter.git', _NEW_DIR],+ capture_output=True, text=True, timeout=120)++ # Copy newer fused_moe.py+ shutil.copy2(os.path.join(_NEW_DIR, 'aiter', 'fused_moe.py'),+ os.path.join(_AITER_DIR, 'aiter', 'fused_moe.py'))++ # Copy safe flydsl files (NOT gemm_kernels.py which needs flydsl.expr)+ flydsl_src = os.path.join(_NEW_DIR, 'aiter', 'ops', 'flydsl')+ flydsl_dst = os.path.join(_AITER_DIR, 'aiter', 'ops', 'flydsl')+ for fname in ['moe_kernels.py', 'utils.py']:+ shutil.copy2(os.path.join(flydsl_src, fname), os.path.join(flydsl_dst, fname))++ # Patch __init__.py version check+ init_path = os.path.join(flydsl_dst, '__init__.py')+ with open(init_path) as f:+ init_src = f.read()+ init_src = re.sub(r'raise ImportError\([^)]*\)', 'pass # version check bypassed', init_src)+ with open(init_path, 'w') as f:+ f.write(init_src)++ # Copy MLIR kernel generators+ kernels_src = os.path.join(flydsl_src, 'kernels')+ kernels_dst = os.path.join(flydsl_dst, 'kernels')+ if os.path.exists(kernels_src):+ os.makedirs(kernels_dst, exist_ok=True)+ for fname in os.listdir(kernels_src):+ if fname.endswith('.py'):+ shutil.copy2(os.path.join(kernels_src, fname), os.path.join(kernels_dst, fname))++ # ========== STEP 3: Source patches ==========+ _FMOE_PATH = os.path.join(_AITER_DIR, 'aiter', 'fused_moe.py')+ with open(_FMOE_PATH, 'r') as f:+ src = f.read()+ src = src.replace('split_k=ksplit', 'split_k=2')+ src = src.replace('splitk=ksplit', 'splitk=2')++ # Minimal block_m override+ bm_marker = 'def get_block_size_M(token, topk, expert, inter_dim):'+ if bm_marker in src:+ dec_search = src.rfind('@functools.lru_cache', 0, src.index(bm_marker))+ start = dec_search if dec_search >= 0 else src.index(bm_marker)+ lines_bm = src[src.index(bm_marker):].split('\n')+ end_offset = 0; found_body = False+ for i, line in enumerate(lines_bm):+ if i == 0: end_offset += len(line) + 1; continue+ stripped = line.strip()+ if stripped == '' or stripped.startswith('#'): end_offset += len(line) + 1; continue+ if found_body and (not line.startswith(' ') and not line.startswith('\t') and stripped != ''): break+ if line.startswith(' ') or line.startswith('\t'): found_body = True+ end_offset += len(line) + 1+ end = src.index(bm_marker) + end_offset+ new_bm = '''@functools.lru_cache(maxsize=2048)+ def get_block_size_M(token, topk, expert, inter_dim):+ _ov = {(512,9,33,512): 128}key = (token, topk, expert, inter_dim)- if key in _bm_ov: return _bm_ov[key]- cu = _fmoe.get_cu_num(); tn = 128; tgN = (inter_dim + tn - 1) // tn+ if key in _ov: return _ov[key]+ cu_num = get_cu_num(); tileN = 128; tgN = (inter_dim + tileN - 1) // tileNtmp = []for el in [32, 64, 128]:- mnt = token * topk + expert * el - topk- tg = tgN * (mnt + el - 1) // el- tmp.append(((tg + cu - 1) // cu, cu - tg % cu, el))+ mnt = token * topk + expert * el - topk; tg = tgN * (mnt + el - 1) // el+ tmp.append(((tg + cu_num - 1) // cu_num, cu_num - tg % cu_num, el))return sorted(tmp, key=lambda x: x[:2])[0][-1]- _fmoe.get_block_size_M = _bm- try: _fmoe.get_2stage_cfgs.cache_clear()- except: pass+ '''+ src = src[:start] + new_bm + src[end:]- # Sort caching- _orig_moe_sorting = _fmoe.moe_sorting- _sort_cache = {}- def _cached_moe_sorting(topk_ids, topk_weights, num_experts, model_dim, dtype, block_m, *args, **kwargs):- key = (topk_ids.data_ptr(), topk_ids.shape[0], num_experts, model_dim, block_m)- if key in _sort_cache:- cached = _sort_cache[key]- cached[4].zero_()- return cached- result = _orig_moe_sorting(topk_ids, topk_weights, num_experts, model_dim, dtype, block_m, *args, **kwargs)- _sort_cache[key] = result- return result- _fmoe.moe_sorting = _cached_moe_sorting+ # Append FlyDSL stage1 + stage2 wrappers+ tail = r'''- # Quant caching- try:- _orig_quant = _fmoe.fused_dynamic_mxfp4_quant_moe_sort- _quant_cache = {}- def _cached_quant(x, sorted_ids, num_valid_ids, token_num, topk, *args, **kwargs):- key = (x.data_ptr(), x.shape[0], sorted_ids.data_ptr())- if key in _quant_cache:- return _quant_cache[key]- result = _orig_quant(x, sorted_ids, num_valid_ids, token_num, topk, *args, **kwargs)- _quant_cache[key] = result- return result- _fmoe.fused_dynamic_mxfp4_quant_moe_sort = _cached_quant- P("quant caching enabled")- except Exception as e:- P(f"quant cache: {e}")+ # v913: FlyDSL BOTH stages+ def _v913_fly_s1(hidden_states, w1, w2, sorted_token_ids, sorted_expert_ids, num_valid_ids, out, topk, w1_scale=None, a1_scale=None, sorted_weights=None, **_kw):+ from aiter.ops.flydsl.moe_kernels import flydsl_moe_stage1+ flydsl_moe_stage1(a=hidden_states, w1=w1, sorted_token_ids=sorted_token_ids,+ sorted_expert_ids=sorted_expert_ids, num_valid_ids=num_valid_ids, out=out, topk=topk,+ tile_m=32, tile_n=256, tile_k=128, a_dtype="fp4", b_dtype="fp4", out_dtype="bf16",+ act="silu", w1_scale=w1_scale, a1_scale=a1_scale, sorted_weights=sorted_weights)+ return out # flydsl writes in-place, but caller expects return value- _fly = [False]; _E = [0]+ def _v913_fly_s2_direct(inter_states, w1, w2, sorted_token_ids, sorted_expert_ids, num_valid_ids, out, topk, w2_scale=None, a2_scale=None, sorted_weights=None, **_kw):+ from aiter.ops.flydsl.moe_kernels import flydsl_moe_stage2+ flydsl_moe_stage2(inter_states=inter_states, w2=w2, sorted_token_ids=sorted_token_ids,+ sorted_expert_ids=sorted_expert_ids, num_valid_ids=num_valid_ids, out=out, topk=topk,+ tile_m=16, tile_n=256, tile_k=128, a_dtype="fp4", b_dtype="fp4", out_dtype="bf16",+ mode="direct", w2_scale=w2_scale, a2_scale=a2_scale, sorted_weights=sorted_weights)- def _fs2(inter_states, w1, w2, sorted_token_ids, sorted_expert_ids, num_valid_ids, out, topk, w2_scale=None, a2_scale=None, sorted_weights=None, **_kw):+ def _v913_fly_s2_atomic(inter_states, w1, w2, sorted_token_ids, sorted_expert_ids, num_valid_ids, out, topk, w2_scale=None, a2_scale=None, sorted_weights=None, **_kw):from aiter.ops.flydsl.moe_kernels import flydsl_moe_stage2- # tile_m=16 for ALL shapes (proven better for E=33)- flydsl_moe_stage2(inter_states=inter_states, w2=w2, sorted_token_ids=sorted_token_ids, sorted_expert_ids=sorted_expert_ids, num_valid_ids=num_valid_ids, out=out, topk=topk, tile_m=16, tile_n=128, tile_k=128, a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", mode="atomic", w2_scale=w2_scale, a2_scale=a2_scale, sorted_weights=sorted_weights)+ flydsl_moe_stage2(inter_states=inter_states, w2=w2, sorted_token_ids=sorted_token_ids,+ sorted_expert_ids=sorted_expert_ids, num_valid_ids=num_valid_ids, out=out, topk=topk,+ tile_m=16, tile_n=256, tile_k=128, a_dtype="fp4", b_dtype="fp4", out_dtype="bf16",+ mode="atomic", w2_scale=w2_scale, a2_scale=a2_scale, sorted_weights=sorted_weights)- _og = _fmoe.get_2stage_cfgs+ _v913_orig_g2sc = get_2stage_cfgs+ try: _v913_orig_g2sc.cache_clear()+ except: pass+ _v913_fly_ready = [False]+ _v913_s1_ready = [False]+@functools.lru_cache(maxsize=2048)- def _pg(*a, **kw):- md = _og(*a, **kw)- if _fly[0] and not md.run_1stage and md.stage2 is not None:- md.stage2 = functools.partial(_fs2)+ def _v913_g2sc(*a, **kw):+ md = _v913_orig_g2sc(*a, **kw)+ if len(a) >= 5:+ E_val = a[4]; bs_val = a[1]+ if E_val <= 100 and bs_val >= 512:+ md.use_non_temporal_load = True+ # Replace stage1 with FlyDSL (if compiled)+ if _v913_s1_ready[0] and not md.run_1stage and md.stage1 is not None:+ md.stage1 = functools.partial(_v913_fly_s1)+ elif not md.run_1stage and md.stage1 is not None:+ _orig_s1 = md.stage1+ def _s1w(*aa, **kk):+ kk['splitk'] = 2+ return _orig_s1(*aa, **kk)+ md.stage1 = _s1w+ # Replace stage2 with FlyDSL+ if _v913_fly_ready[0] and not md.run_1stage and md.stage2 is not None:+ E_val = a[4] if len(a) >= 5 else 0+ md.stage2 = functools.partial(_v913_fly_s2_atomic if E_val > 100 else _v913_fly_s2_direct)return md- _fmoe.get_2stage_cfgs = _pg+ get_2stage_cfgs = _v913_g2sc- def _cf():- try:- from aiter.ops.flydsl.moe_kernels import _get_compiled_stage2 as gc- gc(model_dim=7168, inter_dim=256, experts=257, topk=9, tile_m=16, tile_n=128, tile_k=128, doweight=True, a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", accumulate=True)- for d in [512, 2048]:- gc(model_dim=7168, inter_dim=d, experts=33, topk=9, tile_m=16, tile_n=128, tile_k=128, doweight=True, a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", accumulate=True)- _fly[0] = True; P("flydsl ready (v209)")- except Exception as e: P(f"flydsl FAIL: {e}")+ import sys as _s+ print("[v913] FlyDSL BOTH stages patched", file=_s.stderr)+ '''+ src += tail+ with open(_FMOE_PATH, 'w') as f:+ f.write(src)- _w = [False]- def _warmup():- if _w[0]: return- _w[0] = True; _cf()- for bs, nr, ns, dh, de, nk in [(2,256,1,7168,256,8),(2,32,1,7168,512,8),(2,32,1,7168,2048,8)]:- E = nr+ns; tk = nk+ns; dhp = ((dh+255)//256)*256; dep = ((de+255)//256)*256- h = torch.randn(bs, dh, dtype=torch.bfloat16, device="cuda")- w1 = torch.empty(E, 2*dep, dhp//2, dtype=torch.float4_e2m1fn_x2, device="cuda")- w2 = torch.empty(E, dhp, dep//2, dtype=torch.float4_e2m1fn_x2, device="cuda")- s1 = torch.empty(E, 2*dep, dhp//32, dtype=torch.float8_e8m0fnu, device="cuda")- s2 = torch.empty(E, dhp, dep//32, dtype=torch.float8_e8m0fnu, device="cuda")- tw = torch.ones(bs, tk, dtype=torch.float32, device="cuda"); ti = torch.zeros(bs, tk, dtype=torch.int32, device="cuda")- for t in range(bs):- for k in range(nk): ti[t,k]=k%nr- for k in range(ns): ti[t,nk+k]=nr+k+ # ========== STEP 4: Import ==========+ from aiter import ActivationType, QuantType+ from aiter.fused_moe import fused_moe+ import aiter.fused_moe as _fmoe+ from task import input_t, output_t++ # ========== STEP 5: Pre-compile FlyDSL ==========+ try:+ from aiter.ops.flydsl.moe_kernels import _get_compiled_stage1, _get_compiled_stage2++ # Stage1 for all shapes+ for inter, exp in [(256, 257), (512, 33), (2048, 33)]:try:- _E[0]=E- fused_moe(h,w1,w2,tw,ti,activation=ActivationType.Silu,quant_type=QuantType.per_1x32,w1_scale=s1,w2_scale=s2,hidden_pad=dhp-dh,intermediate_pad=dep-de)- torch.cuda.synchronize()- except Exception as e: P(f"WF: {e}")- P("warmup done (v209)")- _warmup()+ _get_compiled_stage1(model_dim=7168, inter_dim=inter, experts=exp, topk=9,+ tile_m=32, tile_n=256, tile_k=128, doweight=True,+ a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", act="silu")+ print(f"[v913] Stage1 compiled: inter={inter} E={exp}", file=sys.stderr)+ except Exception as e:+ print(f"[v913] Stage1 FAILED inter={inter} E={exp}: {str(e)[:100]}", file=sys.stderr)+ _fmoe._v913_s1_ready[0] = True+ print("[v913] FlyDSL STAGE1 ENABLED!", file=sys.stderr)++ # Stage2 for all shapes+ _get_compiled_stage2(model_dim=7168, inter_dim=256, experts=257, topk=9,+ tile_m=16, tile_n=256, tile_k=128, doweight=True,+ a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", accumulate=True)+ try:+ _get_compiled_stage2(model_dim=7168, inter_dim=256, experts=257, topk=9,+ tile_m=16, tile_n=256, tile_k=128, doweight=True,+ a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", accumulate=True, mode="atomic")+ except: pass+ for d in [512, 2048]:+ _get_compiled_stage2(model_dim=7168, inter_dim=d, experts=33, topk=9,+ tile_m=16, tile_n=256, tile_k=128, doweight=True,+ a_dtype="fp4", b_dtype="fp4", out_dtype="bf16", accumulate=True)+ _fmoe._v913_fly_ready[0] = True+ print("[v913] FlyDSL STAGE2 ENABLED!", file=sys.stderr)+ except Exception as e:+ print(f"[v913] Pre-compile failed: {e}", file=sys.stderr)+ import traceback; traceback.print_exc(file=sys.stderr)++ # Per-shape warmup+ _warmed = set()+ def _warmup(data):+ (hs, guw, dw, guws, dws, guw_sh, dw_sh, guws_sh, dws_sh, tw, ti, cfg) = data+ key = (cfg["bs"], cfg["n_routed_experts"], cfg["d_expert"])+ if key in _warmed: return+ _warmed.add(key)+ try:+ _ = fused_moe(hs[:2], guw_sh, dw_sh, tw[:2], ti[:2],+ activation=ActivationType.Silu, quant_type=QuantType.per_1x32,+ w1_scale=guws_sh, w2_scale=dws_sh,+ hidden_pad=cfg["d_hidden_pad"]-cfg["d_hidden"],+ intermediate_pad=cfg["d_expert_pad"]-cfg["d_expert"])+ torch.cuda.synchronize()+ except: pass+def custom_kernel(data: input_t) -> output_t:- (hs,guw,dw,guws,dws,guw_sh,dw_sh,guws_sh,dws_sh,tw,ti,cfg) = data- _E[0] = cfg["n_routed_experts"] + cfg["n_shared_experts"]- return fused_moe(hs, guw_sh, dw_sh, tw, ti, activation=ActivationType.Silu,- quant_type=QuantType.per_1x32, w1_scale=guws_sh, w2_scale=dws_sh,- hidden_pad=cfg["d_hidden_pad"]-cfg["d_hidden"],- intermediate_pad=cfg["d_expert_pad"]-cfg["d_expert"])+ _warmup(data)+ (hs, guw, dw, guws, dws, guw_sh, dw_sh, guws_sh, dws_sh, tw, ti, cfg) = data+ return fused_moe(hs, guw_sh, dw_sh, tw, ti,+ activation=ActivationType.Silu, quant_type=QuantType.per_1x32,+ w1_scale=guws_sh, w2_scale=dws_sh,+ hidden_pad=cfg["d_hidden_pad"]-cfg["d_hidden"],+ intermediate_pad=cfg["d_expert_pad"]-cfg["d_expert"])
scrolls · 327 diff lines total
Best evidence level for this revision: reported
JSON