submission 754008

import os 
os.environ['PYTORCH_ROCM_ARCH'] = 'gfx950'
NUM_HEADS = 16
NUM_KV_HEADS = 1
KV_LORA_RANK = 512
QK_ROPE_HEAD_DIM = 64
QK_HEAD_DIM = KV_LORA_RANK + QK_ROPE_HEAD_DIM   # 576
V_HEAD_DIM = KV_LORA_RANK                        # 512
PAGE_SIZE = 1
NUM_KV_SPLITS = 32


SM_SCALE = QK_HEAD_DIM ** -0.5
SM_SCALE_LOG2 = 0.06011229337


from torch.utils.cpp_extension import load_inline
from task import input_t, output_t
CPP_WRAPPER = """
void mla_ksplit(size_t batch_size, size_t split_size, torch::Tensor q, torch::Tensor kv, torch::Tensor q_scale, torch::Tensor kv_scale, torch::Tensor output, torch::Tensor sum);
"""

CUDA_SRC = """
#include <hip/amd_detail/amd_hip_fp8.h>
#include <hip/amd_detail/amd_hip_bf16.h>

using fp8x4 = uint32_t;

using bf16x2 = __attribute__((__vector_size__(2 * sizeof(__bf16)))) __bf16;
using i16x4 = __attribute__((__vector_size__(4 * sizeof(short)))) short;
using f32x4 = __attribute__((__vector_size__(4 * sizeof(float)))) float;

typedef fp8x4 (*qkv_t)[16][36][4];

#define SM_SCALE_LOG2 0.06011229337f

__device__ static i16x4 convert4_f32_to_i16(f32x4 x) {
    __hip_bfloat16 tmp[4] = { 
        (__hip_bfloat16)x[0], 
        (__hip_bfloat16)x[1], 
        (__hip_bfloat16)x[2], 
        (__hip_bfloat16)x[3], 
    };
    return *(i16x4*)tmp;
}

__device__ static i16x4 pack_fp8x4_to_i16x4(fp8x4 v, float scale) {
    bf16x2 tmp[2] = 
    {
        __builtin_amdgcn_cvt_scalef32_pk_bf16_fp8(v, scale, false),
        __builtin_amdgcn_cvt_scalef32_pk_bf16_fp8(v, scale, true), 
    };
    return *(i16x4*)tmp;
}



__launch_bounds__(256, 4)
__global__ void mla_ksplit_kernel(
    const qkv_t __restrict__ q,
    const qkv_t __restrict__ kv,
    const float* __restrict__ q_scale_ptr,
    const float* __restrict__ kv_scale_ptr,
    i16x4 (* __restrict__ output)[16][32][4],
    __hip_bfloat16 * __restrict__ out_sum,       
    const size_t numkgroup
) {
    fp8x4 q_buf[8];
    f32x4 result[8];
    __shared__ fp8x4 kv_buf[2][32][64];
    __shared__ i16x4 kv_bf16_buf[2][32][64];
    __shared__ f32x4 psum_buf[5][64];
    const size_t bID = blockIdx.x + blockIdx.y * gridDim.x;
    const size_t trID = (threadIdx.x & 3) << 4 | threadIdx.x >> 2;
    const size_t offset = bID * numkgroup;
    float q_scale = *q_scale_ptr;
    float kv_scale = *kv_scale_ptr;
    #pragma unroll
    for (size_t i = 0; i < 8; ++i) {
        size_t j = i + threadIdx.y * 8;
        q_buf[i] = q[blockIdx.y][threadIdx.x & 15][j][threadIdx.x >> 4];
        result[i] = { 0.0f };
    }

    fp8x4 q_rope = q[blockIdx.y][threadIdx.x & 15][32 + threadIdx.y][threadIdx.x >> 4];

    for (size_t i = 0; i < 8; ++i) {
        size_t j = i + threadIdx.y * 8;
        fp8x4 v = kv[offset][threadIdx.x & 15][j][threadIdx.x >> 4];
        kv_buf[0][j][threadIdx.x] = v;
        kv_bf16_buf[0][j][threadIdx.x] = pack_fp8x4_to_i16x4(v, kv_scale);
    }

    float sum = 0.0f;
    for (size_t n = 0; n < numkgroup; ++n) {
        size_t m = n & 1;

        f32x4 psum = __builtin_amdgcn_mfma_f32_16x16x32_fp8_fp8((int64_t)kv[offset + n][threadIdx.x & 15][32 + threadIdx.y][threadIdx.x >> 4], (int64_t)q_rope, { }, 0, 0, 0);

        if (n < numkgroup - 1)
            for (size_t i = 0; i < 8; ++i) {
                size_t j = i + threadIdx.y * 8;
                fp8x4 v = kv[offset + n + 1][threadIdx.x & 15][j][threadIdx.x >> 4];
                kv_buf[m ^ 1][j][threadIdx.x] = v;
                kv_bf16_buf[m ^ 1][j][threadIdx.x] = pack_fp8x4_to_i16x4(v, kv_scale);
            }

        for (size_t i = 0; i < 4; ++i) {
            size_t j = i + threadIdx.y * 8;
            int64_t x = ((int64_t)kv_buf[m][j + 4][threadIdx.x]) << 32 | kv_buf[m][j][threadIdx.x];
            int64_t y = ((int64_t)q_buf[i + 4]) << 32 | q_buf[i];
            psum = __builtin_amdgcn_mfma_f32_16x16x32_fp8_fp8(x, y, psum, 0, 0, 0);
        }

        psum_buf[threadIdx.y][threadIdx.x] = psum * q_scale * kv_scale;
        __builtin_amdgcn_s_barrier();
        psum_buf[4][threadIdx.x][threadIdx.y] = __builtin_amdgcn_exp2f((psum_buf[0][threadIdx.x][threadIdx.y] + psum_buf[1][threadIdx.x][threadIdx.y] +
            psum_buf[2][threadIdx.x][threadIdx.y] + psum_buf[3][threadIdx.x][threadIdx.y]) * SM_SCALE_LOG2);
        __builtin_amdgcn_s_barrier();
        psum = psum_buf[4][threadIdx.x];
        if (threadIdx.y == 0)
            sum += psum[0] + psum[1] + psum[2] + psum[3];

        i16x4 qkv = convert4_f32_to_i16(psum);
        for (size_t i = 0; i < 8; ++i) {
            size_t j = i + threadIdx.y * 8;
            i16x4 kvt = __builtin_amdgcn_ds_read_tr16_b64_v4i16((__attribute__((address_space(3))) i16x4*)&kv_bf16_buf[m][j][trID]);
            result[i] = __builtin_amdgcn_mfma_f32_16x16x16bf16_1k(kvt, qkv, result[i], 0, 0, 0);
        }
    }

    for (size_t i = 0; i < 8; ++i) {
        size_t j = i + threadIdx.y * 8;
        output[bID][threadIdx.x & 15][j][threadIdx.x >> 4] = convert4_f32_to_i16(result[i]);
    }

    if (threadIdx.y == 0) {
        sum += __shfl_xor_sync(0xFFFFFFFFFFFFFFFF, sum, 16);
        sum += __shfl_xor_sync(0xFFFFFFFFFFFFFFFF, sum, 32);
        if (threadIdx.x < 16) {
            out_sum[bID * 16 + threadIdx.x] = (__hip_bfloat16)sum;
        }
    }
}

void mla_ksplit(size_t batch_size, size_t split_size, torch::Tensor q, torch::Tensor kv, torch::Tensor q_scale, torch::Tensor kv_scale, torch::Tensor output, torch::Tensor sum) {
    size_t by = batch_size;
    size_t bx = split_size;
    size_t numkgroup = kv.size(0) / 4096;
    mla_ksplit_kernel<<<dim3(bx, by), dim3(64, 4), 0, 0>>> ((qkv_t)q.data_ptr(), 
        (qkv_t)kv.data_ptr(),
        (float*)q_scale.data_ptr(),
        (float*)kv_scale.data_ptr(),
        (i16x4(*)[16][32][4])output.data_ptr(), 
        (__hip_bfloat16*)sum.data_ptr(), 
        numkgroup);
}
"""

import os
os.environ["CXX"] = "clang++"

module = load_inline(
    name='mla_ksplit',
    cpp_sources=[CPP_WRAPPER],
    cuda_sources=[CUDA_SRC],
    functions=['mla_ksplit'],
    verbose=True,
    extra_cuda_cflags=["--offload-arch=gfx950", "-std=c++20"],
)

import torch
import torch.nn.functional as F
from task import input_t, output_t
from utils import make_match_reference

from aiter.mla import mla_decode_fwd
from aiter import dtypes as aiter_dtypes
from aiter import get_mla_metadata_info_v1, get_mla_metadata_v1
from aiter.utility.fp4_utils import (
    dynamic_mxfp4_quant,
    mxfp4_to_f32,
    e8m0_to_f32,
)
FP8_DTYPE = aiter_dtypes.fp8

def _make_mla_decode_metadata(
    batch_size: int,
    max_q_len: int,
    nhead: int,
    nhead_kv: int,
    q_dtype: torch.dtype,
    kv_dtype: torch.dtype,
    qo_indptr: torch.Tensor,
    kv_indptr: torch.Tensor,
    kv_last_page_len: torch.Tensor,
    num_kv_splits: int = NUM_KV_SPLITS,
):
    """Allocate and populate work buffers for persistent mla_decode_fwd."""
    info = get_mla_metadata_info_v1(
        batch_size, max_q_len, nhead, q_dtype, kv_dtype,
        is_sparse=False, fast_mode=False,
        num_kv_splits=num_kv_splits, intra_batch_mode=True,
    )
    work = [torch.empty(s, dtype=t, device="cuda") for s, t in info]
    (work_metadata, work_indptr, work_info_set,
     reduce_indptr, reduce_final_map, reduce_partial_map) = work

    # Populate the metadata buffers
    get_mla_metadata_v1(
        qo_indptr, kv_indptr, kv_last_page_len,
        nhead // nhead_kv,   # num_heads_per_head_k
        nhead_kv,            # num_heads_k
        True,                # is_causal
        work_metadata, work_info_set, work_indptr,
        reduce_indptr, reduce_final_map, reduce_partial_map,
        page_size=PAGE_SIZE,
        kv_granularity=max(PAGE_SIZE, 16),
        max_seqlen_qo=max_q_len,
        uni_seqlen_qo=max_q_len,
        fast_mode=False,
        max_split_per_batch=num_kv_splits,
        intra_batch_mode=True,
        dtype_q=q_dtype,
        dtype_kv=kv_dtype,
    )

    return {
        "work_meta_data": work_metadata,
        "work_indptr": work_indptr,
        "work_info_set": work_info_set,
        "reduce_indptr": reduce_indptr,
        "reduce_final_map": reduce_final_map,
        "reduce_partial_map": reduce_partial_map,
    }


# ---------------------------------------------------------------------------
# Aiter reference kernel (decode only)
# ---------------------------------------------------------------------------

def _aiter_mla_decode(
    q: torch.Tensor,
    kv_buffer: torch.Tensor,
    qo_indptr: torch.Tensor,
    kv_indptr: torch.Tensor,
    config: dict,
    q_scale: torch.Tensor | None = None,
    kv_scale: torch.Tensor | None = None,
) -> torch.Tensor:
    """
    MLA decode attention using aiter persistent-mode kernel.

    Supports multiple Q/KV dtype combinations:
      - Q_DTYPE="fp8":  fp8 Q + fp8 KV (a8w8) — fastest on MI355X
      - Q_DTYPE="bf16": bf16 Q + bf16 KV (a16w16) — highest precision

    q:          (total_q, num_heads, 576)  fp8 or bf16
    kv_buffer:  (total_kv, 1, 576)         fp8 or bf16
    q_scale:    scalar float32 (required for fp8 Q, None for bf16)
    kv_scale:   scalar float32 (required for fp8 KV, None for bf16)
    """
    batch_size = config["batch_size"]
    nq = config["num_heads"]
    nkv = config["num_kv_heads"]
    dq = config["qk_head_dim"]
    dv = config["v_head_dim"]
    q_seq_len = config["q_seq_len"]
    total_kv_len = int(kv_indptr[-1].item())

    # Reshape kv_buffer to 4D for aiter: (total_kv, page_size, nhead_kv, dim)
    kv_buffer_4d = kv_buffer.view(kv_buffer.shape[0], PAGE_SIZE, nkv, kv_buffer.shape[-1])

    max_q_len = q_seq_len
    kv_indices = torch.arange(total_kv_len, dtype=torch.int32, device="cuda")
    kv_last_page_len = (kv_indptr[1:] - kv_indptr[:-1]).to(torch.int32)
    meta = _make_mla_decode_metadata(
        batch_size, max_q_len, nq, nkv,
        q.dtype, kv_buffer.dtype,
        qo_indptr, kv_indptr, kv_last_page_len,
        num_kv_splits=NUM_KV_SPLITS,
    )

    o = torch.empty((q.shape[0], nq, dv), dtype=torch.bfloat16, device="cuda")
    mla_decode_fwd(
        q.view(-1, nq, dq),
        kv_buffer_4d,
        o,
        qo_indptr,
        kv_indptr,
        kv_indices,
        kv_last_page_len,
        max_q_len,
        page_size=PAGE_SIZE,
        nhead_kv=nkv,
        sm_scale=SM_SCALE,
        logit_cap=0.0,
        num_kv_splits=NUM_KV_SPLITS,
        q_scale=q_scale,
        kv_scale=kv_scale,
        intra_batch_mode=True,
        **meta,
    )
    return o



from torch.utils.cpp_extension import load_inline

from aiter import dtypes as aiter_dtypes

FP8_DTYPE = aiter_dtypes.fp8

def quantize_fp8(tensor: torch.Tensor) -> tuple[torch.Tensor, torch.Tensor]:
    """
    Dynamic per-tensor FP8 quantization (following sglang scaled_fp8_quant).

    Args:
        tensor: bf16 tensor to quantize

    Returns:
        (fp8_tensor, scale) where scale is a scalar float32 tensor.
        Dequantize: fp8_tensor.to(bf16) * scale
    """
    finfo = torch.finfo(FP8_DTYPE)
    amax = tensor.abs().amax().clamp(min=1e-12)
    scale = amax / finfo.max
    fp8_tensor = (tensor / scale).clamp(min=finfo.min, max=finfo.max).to(FP8_DTYPE)
    return fp8_tensor, scale.to(torch.float32).reshape(1)

def mla(batch_size:int, q: torch.tensor, kv_buffer: torch.tensor, kv_scale: torch.tensor) -> torch.tensor:
    split_size = 256 // batch_size
    q_buffer, q_scale = quantize_fp8(q)
    output = torch.empty(batch_size, split_size, 16, 512, dtype=q.dtype, device=q_buffer.device)
    sum = torch.empty(batch_size, split_size, 16, 1, dtype=q.dtype, device=q_buffer.device)
    module.mla_ksplit(batch_size, split_size, q_buffer, kv_buffer, q_scale, kv_scale, output, sum)
    return (output.sum(dim=1) * sum.sum(dim=1).reciprocal_()).squeeze()

mla_model = torch.compile(mla, backend="inductor")

def custom_kernel(data: input_t) -> output_t:
    q, kv_data, qo_indptr, kv_indptr, config = data
    kv_buffer = kv_data["bf16"]
    batch_size = config["batch_size"]
    kv_buffer, kv_scale = kv_data["fp8"]
    if kv_buffer.shape[0] < 2097152:
        return mla_model(batch_size, q, kv_buffer, kv_scale)
    else:
        q_input, q_scale = quantize_fp8(q)
        return _aiter_mla_decode(
            q_input, kv_buffer, qo_indptr, kv_indptr, config,
            q_scale=q_scale, kv_scale=kv_scale,
        )