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claude-opus-4-1 / tritond18c66

claude-opus-4-1_triton_d18c66 · claude-opus-4-1-20250805 · triton · Apache-2.0

Use it

Vendorable · source mirrored · Apache-2.0View source →

No package. Vendor the mirrored source: 113 lines, Apache-2.0, pinned at da91508.

main.py
curl "https://kernelindex.com/api/v1/implementations/flashinfer-claude-opus-4-1-triton-d18c66?include=source"
interfacetriton
revisionda915083d4c7
symbolrun
pathmain.py
Compatibility
measured onNVIDIA B200
declared hardwareNVIDIA B200
architecturessm_100
dtypesfp16

Benchmark evidence

43 measurements across 1 GPU, fastest first.

Operation / workload
Hardware
Latency
Rank
Observed
GEMM n4096 k4096fp16 · [2, 4096]
NVIDIA B200
68.7µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [8, 4096]
NVIDIA B200
68.7µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [7, 4096]
NVIDIA B200
68.7µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [24, 4096]
NVIDIA B200
68.8µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [15, 4096]
NVIDIA B200
68.8µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [4, 4096]
NVIDIA B200
68.9µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [40, 4096]
NVIDIA B200
68.9µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [16, 4096]
NVIDIA B200
69.0µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [56, 4096]
NVIDIA B200
69.0µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [72, 4096]
NVIDIA B200
69.1µs
#5 of 7
2025-10-16
Show all 43 measurements ›
GEMM n4096 k4096fp16 · [35, 4096]
NVIDIA B200
69.1µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [32, 4096]
NVIDIA B200
69.1µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [48, 4096]
NVIDIA B200
69.2µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [88, 4096]
NVIDIA B200
69.2µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [64, 4096]
NVIDIA B200
69.2µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [70, 4096]
NVIDIA B200
69.2µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [80, 4096]
NVIDIA B200
69.3µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [96, 4096]
NVIDIA B200
69.5µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [144, 4096]
NVIDIA B200
69.6µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [136, 4096]
NVIDIA B200
69.6µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [152, 4096]
NVIDIA B200
69.6µs
#6 of 8
2025-10-16
GEMM n4096 k4096fp16 · [104, 4096]
NVIDIA B200
69.7µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [160, 4096]
NVIDIA B200
69.7µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [176, 4096]
NVIDIA B200
69.7µs
#6 of 8
2025-10-16
GEMM n4096 k4096fp16 · [168, 4096]
NVIDIA B200
69.7µs
#6 of 8
2025-10-16
GEMM n4096 k4096fp16 · [184, 4096]
NVIDIA B200
69.7µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [192, 4096]
NVIDIA B200
69.7µs
#6 of 8
2025-10-16
GEMM n4096 k4096fp16 · [216, 4096]
NVIDIA B200
69.7µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [200, 4096]
NVIDIA B200
69.7µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [208, 4096]
NVIDIA B200
69.7µs
#6 of 9
2025-10-16
GEMM n4096 k4096fp16 · [224, 4096]
NVIDIA B200
69.8µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [112, 4096]
NVIDIA B200
70.0µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [1, 4096]
NVIDIA B200
70.0µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [232, 4096]
NVIDIA B200
70.1µs
#6 of 8
2025-10-16
GEMM n4096 k4096fp16 · [120, 4096]
NVIDIA B200
70.1µs
#6 of 8
2025-10-16
GEMM n4096 k4096fp16 · [240, 4096]
NVIDIA B200
70.7µs
#5 of 8
2025-10-16
GEMM n4096 k4096fp16 · [128, 4096]
NVIDIA B200
71.0µs
#6 of 9
2025-10-16
GEMM n4096 k4096fp16 · [248, 4096]
NVIDIA B200
71.4µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [256, 4096]
NVIDIA B200
71.8µs
#6 of 9
2025-10-16
GEMM n4096 k4096fp16 · [972, 4096]
NVIDIA B200
73.5µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [2053, 4096]
NVIDIA B200
130.5µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [2379, 4096]
NVIDIA B200
131.8µs
#5 of 7
2025-10-16
GEMM n4096 k4096fp16 · [8192, 4096]
NVIDIA B200
351.9µs
#4 of 8
2025-10-16

Reported · How evidence levels are derived →

Source and license

sourcehttps://huggingface.co/datasets/flashinfer-ai/flashinfer-trace
commitda915083d4c7c5e61aa3005e3d17ae488e0fc71c
revision digestsha256:bca6392921b3b39acf6806b0e8ceb6ca5e3cbf621c551845878c4a3af7906bfb
license declaredApache-2.0
license concludedApache-2.0
authorsclaude-opus-4-1-20250805
imported2026-08-20

Techniques

Extracted from the mirrored source by pattern, never inferred. Each row cites its line.

mmaacc = tl.dot(a, tl.trans(b), acc)
tile-k = 32BLOCK_SIZE_K = 32
tile-m = 128BLOCK_SIZE_M = 128
tile-n = 128BLOCK_SIZE_N = 128

Kernel source

main.py113 lines
import torch
import triton
import triton.language as tl

@triton.jit
def gemm_kernel(
    a_ptr, b_ptr, c_ptr,
    M, N, K,
    stride_am, stride_ak,
    stride_bn, stride_bk,
    stride_cm, stride_cn,
    BLOCK_SIZE_M: tl.constexpr,
    BLOCK_SIZE_N: tl.constexpr,
    BLOCK_SIZE_K: tl.constexpr,
):
    # Program ID
    pid_m = tl.program_id(0)
    pid_n = tl.program_id(1)
    
    # Block starting positions
    offs_m = pid_m * BLOCK_SIZE_M + tl.arange(0, BLOCK_SIZE_M)
    offs_n = pid_n * BLOCK_SIZE_N + tl.arange(0, BLOCK_SIZE_N)
    
    # Initialize accumulator with float32 for better precision
    acc = tl.zeros((BLOCK_SIZE_M, BLOCK_SIZE_N), dtype=tl.float32)
    
    # Main loop over K dimension
    for k in range(0, K, BLOCK_SIZE_K):
        offs_k = k + tl.arange(0, BLOCK_SIZE_K)
        
        # Load A tile [BLOCK_SIZE_M, BLOCK_SIZE_K]
        a_ptrs = a_ptr + (offs_m[:, None] * stride_am + offs_k[None, :] * stride_ak)
        a_mask = (offs_m[:, None] < M) & (offs_k[None, :] < K)
        a = tl.load(a_ptrs, mask=a_mask, other=0.0)
        
        # Load B tile [BLOCK_SIZE_N, BLOCK_SIZE_K] - B is stored as [N, K]
        b_ptrs = b_ptr + (offs_n[:, None] * stride_bn + offs_k[None, :] * stride_bk)
        b_mask = (offs_n[:, None] < N) & (offs_k[None, :] < K)
        b = tl.load(b_ptrs, mask=b_mask, other=0.0)
        
        # Perform matrix multiplication: A @ B.T
        # a is [BLOCK_SIZE_M, BLOCK_SIZE_K]
        # b is [BLOCK_SIZE_N, BLOCK_SIZE_K]
        # We need to compute a @ b.T which gives [BLOCK_SIZE_M, BLOCK_SIZE_N]
        acc = tl.dot(a, tl.trans(b), acc)
    
    # Store result
    c_ptrs = c_ptr + (offs_m[:, None] * stride_cm + offs_n[None, :] * stride_cn)
    c_mask = (offs_m[:, None] < M) & (offs_n[None, :] < N)
    tl.store(c_ptrs, acc.to(tl.float16), mask=c_mask)

def run(A, B):
    # Input validation
    if not torch.cuda.is_available():
        raise RuntimeError("CUDA is not available. This kernel requires a GPU.")
    
    # Store original devices
    a_device = A.device
    b_device = B.device
    
    # Move to GPU if needed
    if A.device.type != 'cuda':
        A = A.cuda()
    if B.device.type != 'cuda':
        B = B.cuda()
    
    # Ensure correct dtypes
    if A.dtype != torch.float16:
        A = A.to(torch.float16)
    if B.dtype != torch.float16:
        B = B.to(torch.float16)
    
    # Get dimensions
    M = A.shape[0]
    N = 4096
    K = 4096
    
    # Validate shapes
    assert A.shape == (M, K), f"Expected A shape ({M}, {K}), got {A.shape}"
    assert B.shape == (N, K), f"Expected B shape ({N}, {K}), got {B.shape}"
    
    # Ensure contiguous memory layout
    A = A.contiguous()
    B = B.contiguous()
    
    # Allocate output
    C = torch.empty((M, N), dtype=torch.float16, device=A.device)
    
    # Block sizes optimized for B200
    BLOCK_SIZE_M = 128
    BLOCK_SIZE_N = 128
    BLOCK_SIZE_K = 32
    
    # Grid dimensions
    grid = (triton.cdiv(M, BLOCK_SIZE_M), triton.cdiv(N, BLOCK_SIZE_N))
    
    # Launch kernel
    gemm_kernel[grid](
        A, B, C,
        M, N, K,
        A.stride(0), A.stride(1),
        B.stride(0), B.stride(1),
        C.stride(0), C.stride(1),
        BLOCK_SIZE_M=BLOCK_SIZE_M,
        BLOCK_SIZE_N=BLOCK_SIZE_N,
        BLOCK_SIZE_K=BLOCK_SIZE_K,
    )
    
    # Move result back to original device if needed
    if a_device.type != 'cuda':
        C = C.cpu()
    
    return C
scrolls · 113 lines total

Source code from FlashInfer-Bench (flashinfer-ai/flashinfer-trace) · Apache-2.0

Best evidence level for this revision: reported

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